Commit a5bde2f9 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add basic support for atomfirmware.h (v3) 



This adds basic support for asics that use atomfirmware.h
to define their vbios tables.

v2: rebase
v3: squash in num scratch reg fix

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarKen Wang <Qingqing.Wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 43bf11bd

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ 
	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \

	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o



# add asic specific block

amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −1
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ extern int amdgpu_vram_page_split; 
#define AMDGPU_IB_POOL_SIZE			16

#define AMDGPU_DEBUGFS_MAX_COMPONENTS		32

#define AMDGPUFB_CONN_LIMIT			4

#define AMDGPU_BIOS_NUM_SCRATCH			8

#define AMDGPU_BIOS_NUM_SCRATCH			16



/* max number of IP instances */

#define AMDGPU_MAX_SDMA_INSTANCES		2
@@ -1312,6 +1312,7 @@ struct amdgpu_device { 
	uint8_t				*bios;

	uint32_t			bios_size;

	struct amdgpu_bo		*stollen_vga_memory;

	uint32_t			bios_scratch_reg_offset;

	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];



	/* Register/doorbell mmio */

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

0 → 100644
+112 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include <drm/drmP.h>

#include <drm/amdgpu_drm.h>

#include "amdgpu.h"

#include "atomfirmware.h"

#include "amdgpu_atomfirmware.h"

#include "atom.h"



#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))



bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)

{

	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

						firmwareinfo);

	uint16_t data_offset;



	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,

					  NULL, NULL, &data_offset)) {

		struct atom_firmware_info_v3_1 *firmware_info =

			(struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +

							   data_offset);



		if (le32_to_cpu(firmware_info->firmware_capability) &

		    ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)

			return true;

	}

	return false;

}



void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)

{

	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

						firmwareinfo);

	uint16_t data_offset;



	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,

					  NULL, NULL, &data_offset)) {

		struct atom_firmware_info_v3_1 *firmware_info =

			(struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +

							   data_offset);



		adev->bios_scratch_reg_offset =

			le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);

	}

}



void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev)

{

	int i;



	for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)

		adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + i);

}



void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev)

{

	int i;



	for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)

		WREG32(adev->bios_scratch_reg_offset + i, adev->bios_scratch[i]);

}



int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)

{

	struct atom_context *ctx = adev->mode_info.atom_context;

	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

						vram_usagebyfirmware);

	uint16_t data_offset;

	int usage_bytes = 0;



	if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {

		struct vram_usagebyfirmware_v2_1 *firmware_usage =

			(struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);



		DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",

			  le32_to_cpu(firmware_usage->start_address_in_kb),

			  le16_to_cpu(firmware_usage->used_by_firmware_in_kb),

			  le16_to_cpu(firmware_usage->used_by_driver_in_kb));



		usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) * 1024;

	}

	ctx->scratch_size_bytes = 0;

	if (usage_bytes == 0)

		usage_bytes = 20 * 1024;

	/* allocate some scratch memory */

	ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);

	if (!ctx->scratch)

		return -ENOMEM;

	ctx->scratch_size_bytes = usage_bytes;

	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h

0 → 100644
+33 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2014 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __AMDGPU_ATOMFIRMWARE_H__

#define __AMDGPU_ATOMFIRMWARE_H__



bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev);

int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);



#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+24 −11
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
#include "amdgpu_i2c.h"

#include "atom.h"

#include "amdgpu_atombios.h"

#include "amdgpu_atomfirmware.h"

#include "amd_pcie.h"

#ifdef CONFIG_DRM_AMDGPU_SI

#include "si.h"
@@ -993,8 +994,13 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev) 
	}



	mutex_init(&adev->mode_info.atom_context->mutex);

	if (adev->is_atom_fw) {

		amdgpu_atomfirmware_scratch_regs_init(adev);

		amdgpu_atomfirmware_allocate_fb_scratch(adev);

	} else {

		amdgpu_atombios_scratch_regs_init(adev);

		amdgpu_atombios_allocate_fb_scratch(adev);

	}

	return 0;

}
@@ -1759,9 +1765,14 @@ static int amdgpu_resume(struct amdgpu_device *adev) 


static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)

{

	if (adev->is_atom_fw) {

		if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))

			adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;

	} else {

		if (amdgpu_atombios_has_gpu_virtualization_table(adev))

			adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;

	}

}



/**

 * amdgpu_device_init - initialize the driver
@@ -1931,14 +1942,16 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
		DRM_INFO("GPU post is not needed\n");

	}



	if (!adev->is_atom_fw) {

		/* Initialize clocks */

		r = amdgpu_atombios_get_clock_info(adev);

		if (r) {

			dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");

		goto failed;

			return r;

		}

		/* init i2c buses */

		amdgpu_atombios_i2c_init(adev);

	}



	/* Fence driver */

	r = amdgpu_fence_driver_init(adev);

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