Commit a5a50303 authored by Vitaly Wool's avatar Vitaly Wool Committed by Russell King
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[ARM] 3465/1: [1/3] Support for Philips PNX4008 platform: headers 



Patch from Vitaly Wool

This patch adds kernel headers for PNX4008 ARM platform.
It's basically the same as the previos one, but with the rmk's comments taken into account.

Signed-off-by: default avatarVitaly Wool <vwool@ru.mvista.com>
Signed-off-by: default avatarDmitry Pervushin <dpervushin@gmail.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 51cb21a9

include/asm-arm/arch-pnx4008/clock.h

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/*

 * include/asm-arm/arch-pnx4008/clock.h

 *

 * Clock control driver for PNX4008 - header file

 *

 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>

 *

 * 2005 (c) MontaVista Software, Inc. This file is licensed under

 * the terms of the GNU General Public License version 2. This program

 * is licensed "as is" without any warranty of any kind, whether express

 * or implied.

 */

#ifndef __PNX4008_CLOCK_H__

#define __PNX4008_CLOCK_H__



struct module;

struct clk;



#define PWRMAN_VA_BASE		IO_ADDRESS(PNX4008_PWRMAN_BASE)

#define HCLKDIVCTRL_REG		(PWRMAN_VA_BASE + 0x40)

#define PWRCTRL_REG		(PWRMAN_VA_BASE + 0x44)

#define PLLCTRL_REG		(PWRMAN_VA_BASE + 0x48)

#define OSC13CTRL_REG		(PWRMAN_VA_BASE + 0x4c)

#define SYSCLKCTRL_REG		(PWRMAN_VA_BASE + 0x50)

#define HCLKPLLCTRL_REG		(PWRMAN_VA_BASE + 0x58)

#define USBCTRL_REG		(PWRMAN_VA_BASE + 0x64)

#define SDRAMCLKCTRL_REG	(PWRMAN_VA_BASE + 0x68)

#define MSCTRL_REG		(PWRMAN_VA_BASE + 0x80)

#define BTCLKCTRL		(PWRMAN_VA_BASE + 0x84)

#define DUMCLKCTRL_REG		(PWRMAN_VA_BASE + 0x90)

#define I2CCLKCTRL_REG		(PWRMAN_VA_BASE + 0xac)

#define KEYCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb0)

#define TSCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb4)

#define PWMCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb8)

#define SPICTRL_REG		(PWRMAN_VA_BASE + 0xc4)

#define FLASHCLKCTRL_REG	(PWRMAN_VA_BASE + 0xc8)

#define UART3CLK_REG		(PWRMAN_VA_BASE + 0xd0)

#define UARTCLKCTRL_REG		(PWRMAN_VA_BASE + 0xe4)

#define DMACLKCTRL_REG		(PWRMAN_VA_BASE + 0xe8)

#define AUTOCLK_CTRL		(PWRMAN_VA_BASE + 0xec)

#define JPEGCLKCTRL_REG		(PWRMAN_VA_BASE + 0xfc)



#define AUDIOCONFIG_VA_BASE	IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)

#define DSPPLLCTRL_REG		(AUDIOCONFIG_VA_BASE + 0x60)

#define DSPCLKCTRL_REG		(AUDIOCONFIG_VA_BASE + 0x64)

#define AUDIOCLKCTRL_REG	(AUDIOCONFIG_VA_BASE + 0x68)

#define AUDIOPLLCTRL_REG	(AUDIOCONFIG_VA_BASE + 0x6C)



#define USB_OTG_CLKCTRL_REG	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)



#define VFP9CLKCTRL_REG		IO_ADDRESS(PNX4008_DEBUG_BASE)



#define CLK_RATE_13MHZ 13000

#define CLK_RATE_1MHZ 1000

#define CLK_RATE_208MHZ 208000

#define CLK_RATE_48MHZ 48000

#define CLK_RATE_32KHZ 32



#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */



#endif

include/asm-arm/arch-pnx4008/debug-macro.S

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/* linux/include/asm-arm/arch-pnx4008/debug-macro.S

 *

 * Debugging macro include header

 *

 *  Copyright (C) 1994-1999 Russell King

 *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

*/



		.macro	addruart,rx

		mrc	p15, 0, \rx, c1, c0

		tst	\rx, #1			@ MMU enabled?

		mov	\rx, #0x00090000

		addeq	\rx, \rx, #0x40000000

		addne	\rx, \rx, #0xf4000000

		.endm



		.macro	senduart,rd,rx

		strb	\rd, [\rx, #0x0]

		.endm



#define UART_SHIFT	2

#include <asm/hardware/debug-8250.S>

include/asm-arm/arch-pnx4008/dma.h

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/*

 *  linux/include/asm-arm/arch-pnx4008/dma.h

 *

 *  PNX4008 DMA header file

 *

 *  Author:	Vitaly Wool

 *  Copyright:	MontaVista Software Inc. (c) 2005

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License version 2 as

 *  published by the Free Software Foundation.

 */



#ifndef __ASM_ARCH_DMA_H

#define __ASM_ARCH_DMA_H



#include "platform.h"



#define MAX_DMA_ADDRESS		0xffffffff



#define MAX_DMA_CHANNELS	8



#define DMAC_BASE		IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)

#define DMAC_INT_STAT		(DMAC_BASE + 0x0000)

#define DMAC_INT_TC_STAT	(DMAC_BASE + 0x0004)

#define DMAC_INT_TC_CLEAR	(DMAC_BASE + 0x0008)

#define DMAC_INT_ERR_STAT	(DMAC_BASE + 0x000c)

#define DMAC_INT_ERR_CLEAR	(DMAC_BASE + 0x0010)

#define DMAC_SOFT_SREQ		(DMAC_BASE + 0x0024)

#define DMAC_CONFIG		(DMAC_BASE + 0x0030)

#define DMAC_Cx_SRC_ADDR(c)	(DMAC_BASE + 0x0100 + (c) * 0x20)

#define DMAC_Cx_DEST_ADDR(c)	(DMAC_BASE + 0x0104 + (c) * 0x20)

#define DMAC_Cx_LLI(c)		(DMAC_BASE + 0x0108 + (c) * 0x20)

#define DMAC_Cx_CONTROL(c)	(DMAC_BASE + 0x010c + (c) * 0x20)

#define DMAC_Cx_CONFIG(c)	(DMAC_BASE + 0x0110 + (c) * 0x20)



enum {

	WIDTH_BYTE = 0,

	WIDTH_HWORD,

	WIDTH_WORD

};



enum {

	FC_MEM2MEM_DMA,

	FC_MEM2PER_DMA,

	FC_PER2MEM_DMA,

	FC_PER2PER_DMA,

	FC_PER2PER_DPER,

	FC_MEM2PER_PER,

	FC_PER2MEM_PER,

	FC_PER2PER_SPER

};



enum {

	DMA_INT_UNKNOWN = 0,

	DMA_ERR_INT = 1,

	DMA_TC_INT = 2,

};



enum {

	DMA_BUFFER_ALLOCATED = 1,

	DMA_HAS_LL = 2,

};



enum {

	PER_CAM_DMA_1 = 0,

	PER_NDF_FLASH = 1,

	PER_MBX_SLAVE_FIFO = 2,

	PER_SPI2_REC_XMIT = 3,

	PER_MS_SD_RX_XMIT = 4,

	PER_HS_UART_1_XMIT = 5,

	PER_HS_UART_1_RX = 6,

	PER_HS_UART_2_XMIT = 7,

	PER_HS_UART_2_RX = 8,

	PER_HS_UART_7_XMIT = 9,

	PER_HS_UART_7_RX = 10,

	PER_SPI1_REC_XMIT = 11,

	PER_MLC_NDF_SREC = 12,

	PER_CAM_DMA_2 = 13,

	PER_PRNG_INFIFO = 14,

	PER_PRNG_OUTFIFO = 15,

};



struct pnx4008_dma_ch_ctrl {

	int tc_mask;

	int cacheable;

	int bufferable;

	int priv_mode;

	int di;

	int si;

	int dest_ahb1;

	int src_ahb1;

	int dwidth;

	int swidth;

	int dbsize;

	int sbsize;

	int tr_size;

};



struct pnx4008_dma_ch_config {

	int halt;

	int active;

	int lock;

	int itc;

	int ie;

	int flow_cntrl;

	int dest_per;

	int src_per;

};



struct pnx4008_dma_ll {

	unsigned long src_addr;

	unsigned long dest_addr;

	u32 next_dma;

	unsigned long ch_ctrl;

	struct pnx4008_dma_ll *next;

	int flags;

	void *alloc_data;

	int (*free) (void *);

};



struct pnx4008_dma_config {

	int is_ll;

	unsigned long src_addr;

	unsigned long dest_addr;

	unsigned long ch_ctrl;

	unsigned long ch_cfg;

	struct pnx4008_dma_ll *ll;

	u32 ll_dma;

	int flags;

	void *alloc_data;

	int (*free) (void *);

};



extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);

extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);

extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);



extern int pnx4008_request_channel(char *, int,

				   void (*)(int, int, void *, struct pt_regs *),

				   void *);

extern void pnx4008_free_channel(int);

extern int pnx4008_config_dma(int, int, int);

extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,

				    unsigned long *);

extern int pnx4008_dma_parse_control(unsigned long,

				     struct pnx4008_dma_ch_ctrl *);

extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,

				   unsigned long *);

extern int pnx4008_dma_parse_config(unsigned long,

				    struct pnx4008_dma_ch_config *);

extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);

extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);

extern int pnx4008_dma_ch_enable(int);

extern int pnx4008_dma_ch_disable(int);

extern int pnx4008_dma_ch_enabled(int);

extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,

					 struct pnx4008_dma_ch_ctrl *);

extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,

				       struct pnx4008_dma_ch_ctrl *);



#endif				/* _ASM_ARCH_DMA_H */

include/asm-arm/arch-pnx4008/entry-macro.S

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/*

 * include/asm-arm/arch-pnx4008/entry-macro.S

 *

 * Low-level IRQ helper macros for PNX4008-based platforms

 *

 * 2005-2006 (c) MontaVista Software, Inc.

 * Author: Vitaly Wool <vwool@ru.mvista.com>

 * This file is licensed under  the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#include "platform.h"



#define IO_BASE         0xF0000000

#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)



#define INTRC_MASK			0x00

#define INTRC_RAW_STAT			0x04

#define INTRC_STAT			0x08

#define INTRC_POLAR			0x0C

#define INTRC_ACT_TYPE			0x10

#define INTRC_TYPE			0x14



#define SIC1_BASE_INT   32

#define SIC2_BASE_INT   64



		.macro	disable_fiq

		.endm



		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp

/* decode the MIC interrupt numbers */

		ldr	\base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)

		ldr	\irqstat, [\base, #INTRC_STAT]



		cmp	\irqstat,#1<<16

		movhs	\irqnr,#16

		movlo	\irqnr,#0

		movhs	\irqstat,\irqstat,lsr#16

		cmp	\irqstat,#1<<8

		addhs	\irqnr,\irqnr,#8

		movhs	\irqstat,\irqstat,lsr#8

		cmp	\irqstat,#1<<4

		addhs	\irqnr,\irqnr,#4

		movhs	\irqstat,\irqstat,lsr#4

		cmp	\irqstat,#1<<2

		addhs	\irqnr,\irqnr,#2

		movhs	\irqstat,\irqstat,lsr#2

		cmp	\irqstat,#1<<1

		addhs	\irqnr,\irqnr,#1



/* was there an interrupt ? if not then drop out with EQ status */

		teq	\irqstat,#0

		beq	1003f



/* and now check for extended IRQ reasons */

		cmp	\irqnr,#1

		bls	1003f

		cmp	\irqnr,#30

		blo	1002f



/* IRQ 31,30  : High priority cascade IRQ handle */

/* read the correct SIC */

/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */

/* set the base IRQ number */

		ldreq	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)

		moveq  \irqnr,#SIC1_BASE_INT

		ldrne	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)

		movne   \irqnr,#SIC2_BASE_INT

		ldr	\irqstat, [\base, #INTRC_STAT]

		ldr	\tmp,	  [\base, #INTRC_TYPE]

/* and with inverted mask : low priority interrupts  */

		and	\irqstat,\irqstat,\tmp

		b	1004f



1003:

/* IRQ 1,0  : Low priority cascade IRQ handle */

/* read the correct SIC */

/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/

/* read the correct SIC */

/* set the base IRQ number  */

		ldrne	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)

		movne   \irqnr,#SIC1_BASE_INT

		ldreq	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)

		moveq   \irqnr,#SIC2_BASE_INT

		ldr	\irqstat, [\base, #INTRC_STAT]

		ldr	\tmp,	  [\base, #INTRC_TYPE]

/* and with inverted mask : low priority interrupts  */

		bic	\irqstat,\irqstat,\tmp



1004:



		cmp	\irqstat,#1<<16

		addhs	\irqnr,\irqnr,#16

		movhs	\irqstat,\irqstat,lsr#16

		cmp	\irqstat,#1<<8

		addhs	\irqnr,\irqnr,#8

		movhs	\irqstat,\irqstat,lsr#8

		cmp	\irqstat,#1<<4

		addhs	\irqnr,\irqnr,#4

		movhs	\irqstat,\irqstat,lsr#4

		cmp	\irqstat,#1<<2

		addhs	\irqnr,\irqnr,#2

		movhs	\irqstat,\irqstat,lsr#2

		cmp	\irqstat,#1<<1

		addhs	\irqnr,\irqnr,#1





/* is irqstat not zero */



1002:

/* we assert that irqstat is not equal to zero and return ne status if true*/

		teq	\irqstat,#0

1003:

		.endm





		.macro	irq_prio_table

		.endm

include/asm-arm/arch-pnx4008/gpio.h

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/*

 * include/asm-arm/arch-pnx4008/gpio.h

 *

 * PNX4008 GPIO driver - header file

 *

 * Author: Dmitry Chigirev <source@mvista.com>

 *

 * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:

 * Copyright (c) 2005 Koninklijke Philips Electronics N.V.

 *

 * 2005 (c) MontaVista Software, Inc. This file is licensed under

 * the terms of the GNU General Public License version 2. This program

 * is licensed "as is" without any warranty of any kind, whether express

 * or implied.

 */



#ifndef _PNX4008_GPIO_H_

#define _PNX4008_GPIO_H_





/* Block numbers */

#define GPIO_IN		(0)

#define GPIO_OUT		(0x100)

#define GPIO_BID		(0x200)

#define GPIO_RAM		(0x300)

#define GPIO_MUX		(0x400)



#define GPIO_TYPE_MASK(K) ((K) & 0x700)



/* INPUT GPIOs */

/* GPI */

#define GPI_00		(GPIO_IN | 0)

#define GPI_01		(GPIO_IN | 1)

#define GPI_02   	(GPIO_IN | 2)

#define GPI_03 	 	(GPIO_IN | 3)

#define GPI_04   	(GPIO_IN | 4)

#define GPI_05   	(GPIO_IN | 5)

#define GPI_06   	(GPIO_IN | 6)

#define GPI_07   	(GPIO_IN | 7)

#define GPI_08   	(GPIO_IN | 8)

#define GPI_09   	(GPIO_IN | 9)

#define U1_RX 		(GPIO_IN | 15)

#define U2_HTCS 	(GPIO_IN | 16)

#define U2_RX	 	(GPIO_IN | 17)

#define U3_RX		(GPIO_IN | 18)

#define U4_RX		(GPIO_IN | 19)

#define U5_RX		(GPIO_IN | 20)

#define U6_IRRX 	(GPIO_IN | 21)

#define U7_HCTS 	(GPIO_IN | 22)

#define U7_RX		(GPIO_IN | 23)

/* MISC IN */

#define SPI1_DATIN	(GPIO_IN | 25)

#define DISP_SYNC	(GPIO_IN | 26)

#define SPI2_DATIN	(GPIO_IN | 27)

#define GPI_11  	(GPIO_IN | 28)



#define GPIO_IN_MASK   0x1eff83ff



/* OUTPUT GPIOs */

/* GPO */

#define GPO_00		(GPIO_OUT | 0)

#define GPO_01   	(GPIO_OUT | 1)

#define GPO_02   	(GPIO_OUT | 2)

#define GPO_03 	 	(GPIO_OUT | 3)

#define GPO_04   	(GPIO_OUT | 4)

#define GPO_05   	(GPIO_OUT | 5)

#define GPO_06   	(GPIO_OUT | 6)

#define GPO_07   	(GPIO_OUT | 7)

#define GPO_08		(GPIO_OUT | 8)

#define GPO_09   	(GPIO_OUT | 9)

#define GPO_10   	(GPIO_OUT | 10)

#define GPO_11 	 	(GPIO_OUT | 11)

#define GPO_12   	(GPIO_OUT | 12)

#define GPO_13   	(GPIO_OUT | 13)

#define GPO_14   	(GPIO_OUT | 14)

#define GPO_15   	(GPIO_OUT | 15)

#define GPO_16  	(GPIO_OUT | 16)

#define GPO_17 	 	(GPIO_OUT | 17)

#define GPO_18   	(GPIO_OUT | 18)

#define GPO_19   	(GPIO_OUT | 19)

#define GPO_20   	(GPIO_OUT | 20)

#define GPO_21   	(GPIO_OUT | 21)

#define GPO_22   	(GPIO_OUT | 22)

#define GPO_23   	(GPIO_OUT | 23)



#define GPIO_OUT_MASK   0xffffff



/* BIDIRECTIONAL GPIOs */

/* RAM pins */

#define RAM_D19		(GPIO_RAM | 0)

#define RAM_D20  	(GPIO_RAM | 1)

#define RAM_D21  	(GPIO_RAM | 2)

#define RAM_D22 	(GPIO_RAM | 3)

#define RAM_D23  	(GPIO_RAM | 4)

#define RAM_D24  	(GPIO_RAM | 5)

#define RAM_D25  	(GPIO_RAM | 6)

#define RAM_D26  	(GPIO_RAM | 7)

#define RAM_D27		(GPIO_RAM | 8)

#define RAM_D28  	(GPIO_RAM | 9)

#define RAM_D29  	(GPIO_RAM | 10)

#define RAM_D30 	(GPIO_RAM | 11)

#define RAM_D31  	(GPIO_RAM | 12)



#define GPIO_RAM_MASK   0x1fff



/* I/O pins */

#define GPIO_00  	(GPIO_BID | 25)

#define GPIO_01 	(GPIO_BID | 26)

#define GPIO_02  	(GPIO_BID | 27)

#define GPIO_03  	(GPIO_BID | 28)

#define GPIO_04 	(GPIO_BID | 29)

#define GPIO_05  	(GPIO_BID | 30)



#define GPIO_BID_MASK   0x7e000000



/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */

#define GPIO_SDRAM_SEL 	(GPIO_MUX | 3)



#define GPIO_MUX_MASK   0x8



/* Extraction/assembly macros */

#define GPIO_BIT_MASK(K) ((K) & 0x1F)

#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))

#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))

#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))

#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))

#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))

#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))



extern int pnx4008_gpio_register_pin(unsigned short pin);

extern int pnx4008_gpio_unregister_pin(unsigned short pin);

extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);

extern int pnx4008_gpio_write_pin(unsigned short pin, int output);

extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);

extern int pnx4008_gpio_read_pin_direction(unsigned short pin);

extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);

extern int pnx4008_gpio_read_pin_mux(unsigned short pin);



#endif				/* _PNX4008_GPIO_H_ */

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