Commit a5964396 authored Nov 18, 2015 by Rajmohan Mani Committed by Greg Kroah-Hartman Nov 18, 2015

xhci: Workaround to get Intel xHCI reset working more reliably



Existing Intel xHCI controllers require a delay of 1 mS,
after setting the CMD_RESET bit in command register, before
accessing any HC registers. This allows the HC to complete
the reset operation and be ready for HC register access.
Without this delay, the subsequent HC register access,
may result in a system hang, very rarely.

Verified CherryView / Braswell platforms go through over
5000 warm reboot cycles (which was not possible without
this patch), without any xHCI reset hang.

Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: Joe Lawrence <joe.lawrence@stratus.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 53de9807

drivers/usb/host/xhci.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -175,6 +175,16 @@ int xhci_reset(struct xhci_hcd *xhci)
		command \|= CMD_RESET;
		writel(command, &xhci->op_regs->command);

		/* Existing Intel xHCI controllers require a delay of 1 mS,
		* after setting the CMD_RESET bit, and before accessing any
		* HC registers. This allows the HC to complete the
		* reset operation and be ready for HC register access.
		* Without this delay, the subsequent HC register access,
		* may result in a system hang very rarely.
		*/
		if (xhci->quirks & XHCI_INTEL_HOST)
		udelay(1000);

		ret = xhci_handshake(&xhci->op_regs->command,
		CMD_RESET, 0, 10 * 1000 * 1000);
		if (ret)

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