clk: samsung: exynos5433: Add clocks for CMU_CAM1 domain

  - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0

    which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}

    IPs.

  - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1

    which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.

- reg: physical base address of the controller and length of memory mapped

  region.

		- aclk_cam0_400

		- aclk_cam0_552

	Input clocks for cam1 clock controller:

		- oscclk

		- sclk_isp_uart_cam1

		- sclk_isp_spi1_cam1

		- sclk_isp_spi0_cam1

		- aclk_cam1_333

		- aclk_cam1_400

		- aclk_cam1_552

Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume.

		       <&cmu_top CLK_ACLK_CAM0_552>;

	};

	cmu_cam1: clock-controller@145d0000 {

		compatible = "samsung,exynos5433-cmu-cam1";

		reg = <0x145d0000 0x0b08>;

		#clock-cells = <1>;

		clock-names = "oscclk",

			"sclk_isp_uart_cam1",

			"sclk_isp_spi1_cam1",

			"sclk_isp_spi0_cam1",

			"aclk_cam1_333",

			"aclk_cam1_400",

			"aclk_cam1_552";

		clocks = <&xxti>,

		       <&cmu_top CLK_SCLK_ISP_UART_CAM1>,

		       <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,

		       <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,

		       <&cmu_top CLK_ACLK_CAM1_333>,

		       <&cmu_top CLK_ACLK_CAM1_400>,

		       <&cmu_top CLK_ACLK_CAM1_552>;

	};

Example 3: UART controller node that consumes the clock generated by the clock

	   controller.