Commit a5819b54 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Bjorn Andersson
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tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state



geni serial needs to express a perforamnce state requirement on CX
powerdomain depending on the frequency of the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.

Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Akash Asthana <akashast@codeaurora.org>
Cc: linux-serial@vger.kernel.org
Link: https://lore.kernel.org/r/1592222564-13556-2-git-send-email-rnayak@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent cff80645
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+25 −4
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pm_wakeirq.h>
@@ -963,7 +964,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
		goto out_restart_rx;

	uport->uartclk = clk_rate;
	clk_set_rate(port->se.clk, clk_rate);
	dev_pm_opp_set_rate(uport->dev, clk_rate);
	ser_clk_cfg = SER_CLK_EN;
	ser_clk_cfg |= clk_div << CLK_DIV_SHFT;

@@ -1383,13 +1384,25 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
	if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
		port->cts_rts_swap = true;

	port->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
	if (IS_ERR(port->se.opp_table))
		return PTR_ERR(port->se.opp_table);
	/* OPP table is optional */
	ret = dev_pm_opp_of_add_table(&pdev->dev);
	if (!ret) {
		port->se.has_opp_table = true;
	} else if (ret != -ENODEV) {
		dev_err(&pdev->dev, "invalid OPP table in device tree\n");
		return ret;
	}

	uport->private_data = drv;
	platform_set_drvdata(pdev, port);
	port->handle_rx = console ? handle_rx_console : handle_rx_uart;

	ret = uart_add_one_port(drv, uport);
	if (ret)
		return ret;
		goto err;

	irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
	ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
@@ -1397,7 +1410,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
	if (ret) {
		dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
		uart_remove_one_port(drv, uport);
		return ret;
		goto err;
	}

	/*
@@ -1414,11 +1427,16 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
		if (ret) {
			device_init_wakeup(&pdev->dev, false);
			uart_remove_one_port(drv, uport);
			return ret;
			goto err;
		}
	}

	return 0;
err:
	if (port->se.has_opp_table)
		dev_pm_opp_of_remove_table(&pdev->dev);
	dev_pm_opp_put_clkname(port->se.opp_table);
	return ret;
}

static int qcom_geni_serial_remove(struct platform_device *pdev)
@@ -1426,6 +1444,9 @@ static int qcom_geni_serial_remove(struct platform_device *pdev)
	struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
	struct uart_driver *drv = port->uport.private_data;

	if (port->se.has_opp_table)
		dev_pm_opp_of_remove_table(&pdev->dev);
	dev_pm_opp_put_clkname(port->se.opp_table);
	dev_pm_clear_wake_irq(&pdev->dev);
	device_init_wakeup(&pdev->dev, false);
	uart_remove_one_port(drv, &port->uport);
+4 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ struct geni_icc_path {
 * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl
 * @clk_perf_tbl:	Table of clock frequency input to serial engine clock
 * @icc_paths:		Array of ICC paths for SE
 * @opp_table:		Pointer to the OPP table
 * @has_opp_table:	Specifies if the SE has an OPP table
 */
struct geni_se {
	void __iomem *base;
@@ -56,6 +58,8 @@ struct geni_se {
	unsigned int num_clk_levels;
	unsigned long *clk_perf_tbl;
	struct geni_icc_path icc_paths[3];
	struct opp_table *opp_table;
	bool has_opp_table;
};

/* Common SE registers */