Merge tag 'phy-for-4.6' of...

- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795

	      SoC.

- reg: offset and length of the partial USB 2.0 Host register block.

- reg-names: must be "usb2_host".

- clocks: clock phandle and specifier pair(s).

- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.

Optional properties:

To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are

combined, the device tree node should set HSUSB properties to reg and reg-names

properties. This is because HSUSB has registers to select USB 2.0 host or

peripheral at that channel:

- reg: offset and length of the partial HSUSB register block.

- reg-names: must be "hsusb".

combined, the device tree node should set interrupt properties to use the

channel as USB OTG:

- interrupts: interrupt specifier for the PHY.

Example (R-Car H3):

	usb-phy@ee080200 {

		compatible = "renesas,usb2-phy-r8a7795";

		reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;

		reg-names = "usb2_host", "hsusb";

		reg = <0 0xee080200 0 0x700>;

		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,

			 <&mstp7_clks R8A7795_CLK_HSUSB>;

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;

	};

	usb-phy@ee0a0200 {

		compatible = "renesas,usb2-phy-r8a7795";

		reg = <0 0xee0a0200 0 0x700>;

		reg-names = "usb2_host";

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;

	};

Rockchip specific extensions to the Analogix Display Port PHY

------------------------------------

Required properties:

- compatible : should be one of the following supported values:

	 - "rockchip.rk3288-dp-phy"

- clocks: from common clock binding: handle to dp clock.

	of memory mapped region.

- clock-names: from common clock binding:

	Required elements: "24m"

- rockchip,grf: phandle to the syscon managing the "general register files"

- #phy-cells : from the generic PHY bindings, must be 0;

Example:

edp_phy: edp-phy {

	compatible = "rockchip,rk3288-dp-phy";

	rockchip,grf = <&grf>;

	clocks = <&cru SCLK_EDP_24M>;

	clock-names = "24m";

	#phy-cells = <0>;

};

Rockchip EMMC PHY

-----------------------

Required properties:

 - compatible: rockchip,rk3399-emmc-phy

 - rockchip,grf : phandle to the syscon managing the "general

   register files"

 - #phy-cells: must be 0

 - reg: PHY configure reg address offset in "general

   register files"

Example:

emmcphy: phy {

	compatible = "rockchip,rk3399-emmc-phy";

	rockchip,grf = <&grf>;

	reg = <0xf780>;

	#phy-cells = <0>;

};

	ro		[KNL] Mount root device read-only on boot

	rockchip.usb_uart

			Enable the uart passthrough on the designated usb port

			on Rockchip SoCs. When active, the signals of the

			debug-uart get routed to the D+ and D- pins of the usb

			port and the regular usb controller gets disabled.

	root=		[KNL] Root filesystem

			See name_to_dev_t comment in init/do_mounts.c.

config ARMADA375_USBCLUSTER_PHY

	def_bool y

	depends on MACH_ARMADA_375 || COMPILE_TEST

	depends on OF

	depends on OF && HAS_IOMEM

	select GENERIC_PHY

config PHY_DM816X_USB

	help

	  Enable this to support the Rockchip USB 2.0 PHY.

config PHY_ROCKCHIP_EMMC

	tristate "Rockchip EMMC PHY Driver"

	depends on ARCH_ROCKCHIP && OF

	select GENERIC_PHY

	help

	  Enable this to support the Rockchip EMMC PHY.

config PHY_ROCKCHIP_DP

	tristate "Rockchip Display Port PHY Driver"

	depends on ARCH_ROCKCHIP && OF

	select GENERIC_PHY

	help

	  Enable this to support the Rockchip Display Port PHY.

config PHY_ST_SPEAR1310_MIPHY

	tristate "ST SPEAR1310-MIPHY driver"

	select GENERIC_PHY