Commit a54b19f1 authored by Lionel Landwerlin's avatar Lionel Landwerlin
Browse files

drm/i915/perf: complete whitelisting for OA programming on HSW 



We were missing some registers and also can name one for which we only had
the offset.

Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171110190845.32574-2-lionel.g.landwerlin@intel.com
parent 10bf0a38

drivers/gpu/drm/i915/i915_perf.c

+2 −1
Original line number Diff line number Diff line
@@ -3023,7 +3023,8 @@ static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) 
{

	return gen7_is_valid_mux_addr(dev_priv, addr) ||

		(addr >= 0x25100 && addr <= 0x2FF90) ||

		addr == 0x9ec0;

		(addr >= HSW_MBVID2_NOA0.reg && addr <= HSW_MBVID2_NOA9.reg) ||

		addr == HSW_MBVID2_MISR0.reg;

}



static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)

drivers/gpu/drm/i915/i915_reg.h

+14 −0
Original line number Diff line number Diff line
@@ -1117,6 +1117,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
/* RPC unit config (Gen8+) */

#define RPM_CONFIG	    _MMIO(0x0D08)



/* NOA (HSW) */

#define HSW_MBVID2_NOA0		_MMIO(0x9E80)

#define HSW_MBVID2_NOA1		_MMIO(0x9E84)

#define HSW_MBVID2_NOA2		_MMIO(0x9E88)

#define HSW_MBVID2_NOA3		_MMIO(0x9E8C)

#define HSW_MBVID2_NOA4		_MMIO(0x9E90)

#define HSW_MBVID2_NOA5		_MMIO(0x9E94)

#define HSW_MBVID2_NOA6		_MMIO(0x9E98)

#define HSW_MBVID2_NOA7		_MMIO(0x9E9C)

#define HSW_MBVID2_NOA8		_MMIO(0x9EA0)

#define HSW_MBVID2_NOA9		_MMIO(0x9EA4)



#define HSW_MBVID2_MISR0	_MMIO(0x9EC0)



/* NOA (Gen8+) */

#define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)

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