Merge tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl (a547df99) · Commits · 戴 / test

Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt

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		Broadcom Capri Pin Controller

		This is a pin controller for the Broadcom BCM281xx SoC family, which includes
		BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.

		=== Pin Controller Node ===

		Required Properties:

		- compatible: Must be "brcm,capri-pinctrl".
		- reg: Base address of the PAD Controller register block and the size
		of the block.

		For example, the following is the bare minimum node:

		pinctrl@35004800 {
		compatible = "brcm,capri-pinctrl";
		reg = <0x35004800 0x430>;
		};

		As a pin controller device, in addition to the required properties, this node
		should also contain the pin configuration nodes that client devices reference,
		if any.

		=== Pin Configuration Node ===

		Each pin configuration node is a sub-node of the pin controller node and is a
		container of an arbitrary number of subnodes, called pin group nodes in this
		document.

		Please refer to the pinctrl-bindings.txt in this directory for details of the
		common pinctrl bindings used by client devices, including the definition of a
		"pin configuration node".

		=== Pin Group Node ===

		A pin group node specifies the desired pin mux and/or pin configuration for an
		arbitrary number of pins. The name of the pin group node is optional and not
		used.

		A pin group node only affects the properties specified in the node, and has no
		effect on any properties that are omitted.

		The pin group node accepts a subset of the generic pin config properties. For
		details generic pin config properties, please refer to pinctrl-bindings.txt
		and <include/linux/pinctrl/pinconfig-generic.h>.

		Each pin controlled by this pin controller belong to one of three types:
		Standard, I2C, and HDMI. Each type accepts a different set of pin config
		properties. A list of pins and their types is provided below.

		Required Properties (applicable to all pins):

		- pins: Multiple strings. Specifies the name(s) of one or more pins to
		be configured by this node.

		Optional Properties (for standard pins):

		- function: String. Specifies the pin mux selection. Values
		must be one of: "alt1", "alt2", "alt3", "alt4"
		- input-schmitt-enable: No arguments. Enable schmitt-trigger mode.
		- input-schmitt-disable: No arguments. Disable schmitt-trigger mode.
		- bias-pull-up: No arguments. Pull up on pin.
		- bias-pull-down: No arguments. Pull down on pin.
		- bias-disable: No arguments. Disable pin bias.
		- slew-rate: Integer. Meaning depends on configured pin mux:
		_SCL or _SDA:
		0: Standard(100kbps)& Fast(400kbps) mode
		1: Highspeed (3.4Mbps) mode
		IC_DM or IC_DP:
		0: normal slew rate
		1: fast slew rate
		Otherwise:
		0: fast slew rate
		1: normal slew rate
		- input-enable: No arguements. Enable input (does not affect
		output.)
		- input-disable: No arguements. Disable input (does not affect
		output.)
		- drive-strength: Integer. Drive strength in mA. Valid values are
		2, 4, 6, 8, 10, 12, 14, 16 mA.

		Optional Properties (for I2C pins):

		- function: String. Specifies the pin mux selection. Values
		must be one of: "alt1", "alt2", "alt3", "alt4"
		- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
		pull-up resisitors (1.2k, 1.8k, 2.7k) available
		in parallel for I2C pins, so the valid values
		are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
		- bias-disable: No arguments. Disable pin bias.
		- slew-rate: Integer. Meaning depends on configured pin mux:
		_SCL or _SDA:
		0: Standard(100kbps)& Fast(400kbps) mode
		1: Highspeed (3.4Mbps) mode
		IC_DM or IC_DP:
		0: normal slew rate
		1: fast slew rate
		Otherwise:
		0: fast slew rate
		1: normal slew rate
		- input-enable: No arguements. Enable input (does not affect
		output.)
		- input-disable: No arguements. Disable input (does not affect
		output.)

		Optional Properties (for HDMI pins):

		- function: String. Specifies the pin mux selection. Values
		must be one of: "alt1", "alt2", "alt3", "alt4"
		- slew-rate: Integer. Controls slew rate.
		0: Standard(100kbps)& Fast(400kbps) mode
		1: Highspeed (3.4Mbps) mode
		- input-enable: No arguements. Enable input (does not affect
		output.)
		- input-disable: No arguements. Disable input (does not affect
		output.)

		Example:
		// pin controller node
		pinctrl@35004800 {
		compatible = "brcm,capri-pinctrl";
		reg = <0x35004800 0x430>;

		// pin configuration node
		dev_a_default: dev_a_active {
		//group node defining 1 standard pin
		grp_1 {
		pins = "std_pin1";
		function = "alt1";
		input-schmitt-enable;
		bias-disable;
		slew-rate = <1>;
		drive-strength = <4>;
		};

		// group node defining 2 I2C pins
		grp_2 {
		pins = "i2c_pin1", "i2c_pin2";
		function = "alt2";
		bias-pull-up = <720>;
		input-enable;
		};

		// group node defining 2 HDMI pins
		grp_3 {
		pins = "hdmi_pin1", "hdmi_pin2";
		function = "alt3";
		slew-rate = <1>;
		};

		// other pin group nodes
		...
		};

		// other pin configuration nodes
		...
		};

		In the example above, "dev_a_active" is a pin configuration node with a number
		of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in
		the "pins" property. Thus, the remaining properties in the "grp_1" node applies
		only to this pin, including the following settings:
		- setting pinmux to "alt1"
		- enabling schmitt-trigger (hystersis) mode
		- disabling pin bias
		- setting the slew-rate to 1
		- setting the drive strength to 4 mA
		Note that neither "input-enable" nor "input-disable" was specified - the pinctrl
		subsystem will therefore leave this property unchanged from whatever state it
		was in before applying these changes.

		The "pins" property in the pin group node "grp_2" specifies two pins -
		"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node,
		therefore, applies to both of these pins. The properties include:
		- setting pinmux to "alt2"
		- setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors
		in parallel)
		- enabling both pins' input
		"slew-rate" is not specified in this pin group node, so the slew-rate for these
		pins are left as-is.

		Finally, "grp_3" defines two HDMI pins. The following properties are applied to
		both pins:
		- setting pinmux to "alt3"
		- setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps
		Highspeed mode
		The input is neither enabled or disabled, and is left untouched.

		=== Pin Names and Type ===

		The following are valid pin names and their pin types:

		"adcsync", Standard
		"bat_rm", Standard
		"bsc1_scl", I2C
		"bsc1_sda", I2C
		"bsc2_scl", I2C
		"bsc2_sda", I2C
		"classgpwr", Standard
		"clk_cx8", Standard
		"clkout_0", Standard
		"clkout_1", Standard
		"clkout_2", Standard
		"clkout_3", Standard
		"clkreq_in_0", Standard
		"clkreq_in_1", Standard
		"cws_sys_req1", Standard
		"cws_sys_req2", Standard
		"cws_sys_req3", Standard
		"digmic1_clk", Standard
		"digmic1_dq", Standard
		"digmic2_clk", Standard
		"digmic2_dq", Standard
		"gpen13", Standard
		"gpen14", Standard
		"gpen15", Standard
		"gpio00", Standard
		"gpio01", Standard
		"gpio02", Standard
		"gpio03", Standard
		"gpio04", Standard
		"gpio05", Standard
		"gpio06", Standard
		"gpio07", Standard
		"gpio08", Standard
		"gpio09", Standard
		"gpio10", Standard
		"gpio11", Standard
		"gpio12", Standard
		"gpio13", Standard
		"gpio14", Standard
		"gps_pablank", Standard
		"gps_tmark", Standard
		"hdmi_scl", HDMI
		"hdmi_sda", HDMI
		"ic_dm", Standard
		"ic_dp", Standard
		"kp_col_ip_0", Standard
		"kp_col_ip_1", Standard
		"kp_col_ip_2", Standard
		"kp_col_ip_3", Standard
		"kp_row_op_0", Standard
		"kp_row_op_1", Standard
		"kp_row_op_2", Standard
		"kp_row_op_3", Standard
		"lcd_b_0", Standard
		"lcd_b_1", Standard
		"lcd_b_2", Standard
		"lcd_b_3", Standard
		"lcd_b_4", Standard
		"lcd_b_5", Standard
		"lcd_b_6", Standard
		"lcd_b_7", Standard
		"lcd_g_0", Standard
		"lcd_g_1", Standard
		"lcd_g_2", Standard
		"lcd_g_3", Standard
		"lcd_g_4", Standard
		"lcd_g_5", Standard
		"lcd_g_6", Standard
		"lcd_g_7", Standard
		"lcd_hsync", Standard
		"lcd_oe", Standard
		"lcd_pclk", Standard
		"lcd_r_0", Standard
		"lcd_r_1", Standard
		"lcd_r_2", Standard
		"lcd_r_3", Standard
		"lcd_r_4", Standard
		"lcd_r_5", Standard
		"lcd_r_6", Standard
		"lcd_r_7", Standard
		"lcd_vsync", Standard
		"mdmgpio0", Standard
		"mdmgpio1", Standard
		"mdmgpio2", Standard
		"mdmgpio3", Standard
		"mdmgpio4", Standard
		"mdmgpio5", Standard
		"mdmgpio6", Standard
		"mdmgpio7", Standard
		"mdmgpio8", Standard
		"mphi_data_0", Standard
		"mphi_data_1", Standard
		"mphi_data_2", Standard
		"mphi_data_3", Standard
		"mphi_data_4", Standard
		"mphi_data_5", Standard
		"mphi_data_6", Standard
		"mphi_data_7", Standard
		"mphi_data_8", Standard
		"mphi_data_9", Standard
		"mphi_data_10", Standard
		"mphi_data_11", Standard
		"mphi_data_12", Standard
		"mphi_data_13", Standard
		"mphi_data_14", Standard
		"mphi_data_15", Standard
		"mphi_ha0", Standard
		"mphi_hat0", Standard
		"mphi_hat1", Standard
		"mphi_hce0_n", Standard
		"mphi_hce1_n", Standard
		"mphi_hrd_n", Standard
		"mphi_hwr_n", Standard
		"mphi_run0", Standard
		"mphi_run1", Standard
		"mtx_scan_clk", Standard
		"mtx_scan_data", Standard
		"nand_ad_0", Standard
		"nand_ad_1", Standard
		"nand_ad_2", Standard
		"nand_ad_3", Standard
		"nand_ad_4", Standard
		"nand_ad_5", Standard
		"nand_ad_6", Standard
		"nand_ad_7", Standard
		"nand_ale", Standard
		"nand_cen_0", Standard
		"nand_cen_1", Standard
		"nand_cle", Standard
		"nand_oen", Standard
		"nand_rdy_0", Standard
		"nand_rdy_1", Standard
		"nand_wen", Standard
		"nand_wp", Standard
		"pc1", Standard
		"pc2", Standard
		"pmu_int", Standard
		"pmu_scl", I2C
		"pmu_sda", I2C
		"rfst2g_mtsloten3g", Standard
		"rgmii_0_rx_ctl", Standard
		"rgmii_0_rxc", Standard
		"rgmii_0_rxd_0", Standard
		"rgmii_0_rxd_1", Standard
		"rgmii_0_rxd_2", Standard
		"rgmii_0_rxd_3", Standard
		"rgmii_0_tx_ctl", Standard
		"rgmii_0_txc", Standard
		"rgmii_0_txd_0", Standard
		"rgmii_0_txd_1", Standard
		"rgmii_0_txd_2", Standard
		"rgmii_0_txd_3", Standard
		"rgmii_1_rx_ctl", Standard
		"rgmii_1_rxc", Standard
		"rgmii_1_rxd_0", Standard
		"rgmii_1_rxd_1", Standard
		"rgmii_1_rxd_2", Standard
		"rgmii_1_rxd_3", Standard
		"rgmii_1_tx_ctl", Standard
		"rgmii_1_txc", Standard
		"rgmii_1_txd_0", Standard
		"rgmii_1_txd_1", Standard
		"rgmii_1_txd_2", Standard
		"rgmii_1_txd_3", Standard
		"rgmii_gpio_0", Standard
		"rgmii_gpio_1", Standard
		"rgmii_gpio_2", Standard
		"rgmii_gpio_3", Standard
		"rtxdata2g_txdata3g1", Standard
		"rtxen2g_txdata3g2", Standard
		"rxdata3g0", Standard
		"rxdata3g1", Standard
		"rxdata3g2", Standard
		"sdio1_clk", Standard
		"sdio1_cmd", Standard
		"sdio1_data_0", Standard
		"sdio1_data_1", Standard
		"sdio1_data_2", Standard
		"sdio1_data_3", Standard
		"sdio4_clk", Standard
		"sdio4_cmd", Standard
		"sdio4_data_0", Standard
		"sdio4_data_1", Standard
		"sdio4_data_2", Standard
		"sdio4_data_3", Standard
		"sim_clk", Standard
		"sim_data", Standard
		"sim_det", Standard
		"sim_resetn", Standard
		"sim2_clk", Standard
		"sim2_data", Standard
		"sim2_det", Standard
		"sim2_resetn", Standard
		"sri_c", Standard
		"sri_d", Standard
		"sri_e", Standard
		"ssp_extclk", Standard
		"ssp0_clk", Standard
		"ssp0_fs", Standard
		"ssp0_rxd", Standard
		"ssp0_txd", Standard
		"ssp2_clk", Standard
		"ssp2_fs_0", Standard
		"ssp2_fs_1", Standard
		"ssp2_fs_2", Standard
		"ssp2_fs_3", Standard
		"ssp2_rxd_0", Standard
		"ssp2_rxd_1", Standard
		"ssp2_txd_0", Standard
		"ssp2_txd_1", Standard
		"ssp3_clk", Standard
		"ssp3_fs", Standard
		"ssp3_rxd", Standard
		"ssp3_txd", Standard
		"ssp4_clk", Standard
		"ssp4_fs", Standard
		"ssp4_rxd", Standard
		"ssp4_txd", Standard
		"ssp5_clk", Standard
		"ssp5_fs", Standard
		"ssp5_rxd", Standard
		"ssp5_txd", Standard
		"ssp6_clk", Standard
		"ssp6_fs", Standard
		"ssp6_rxd", Standard
		"ssp6_txd", Standard
		"stat_1", Standard
		"stat_2", Standard
		"sysclken", Standard
		"traceclk", Standard
		"tracedt00", Standard
		"tracedt01", Standard
		"tracedt02", Standard
		"tracedt03", Standard
		"tracedt04", Standard
		"tracedt05", Standard
		"tracedt06", Standard
		"tracedt07", Standard
		"tracedt08", Standard
		"tracedt09", Standard
		"tracedt10", Standard
		"tracedt11", Standard
		"tracedt12", Standard
		"tracedt13", Standard
		"tracedt14", Standard
		"tracedt15", Standard
		"txdata3g0", Standard
		"txpwrind", Standard
		"uartb1_ucts", Standard
		"uartb1_urts", Standard
		"uartb1_urxd", Standard
		"uartb1_utxd", Standard
		"uartb2_urxd", Standard
		"uartb2_utxd", Standard
		"uartb3_ucts", Standard
		"uartb3_urts", Standard
		"uartb3_urxd", Standard
		"uartb3_utxd", Standard
		"uartb4_ucts", Standard
		"uartb4_urts", Standard
		"uartb4_urxd", Standard
		"uartb4_utxd", Standard
		"vc_cam1_scl", I2C
		"vc_cam1_sda", I2C
		"vc_cam2_scl", I2C
		"vc_cam2_sda", I2C
		"vc_cam3_scl", I2C
		"vc_cam3_sda", I2C

Documentation/devicetree/bindings/pinctrl/fsl,imx25-pinctrl.txt

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		* Freescale IMX25 IOMUX Controller

		Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
		and usage.

		CONFIG bits definition:
		PAD_CTL_HYS (1 << 8)
		PAD_CTL_PKE (1 << 7)
		PAD_CTL_PUE (1 << 6)
		PAD_CTL_PUS_100K_DOWN (0 << 4)
		PAD_CTL_PUS_47K_UP (1 << 4)
		PAD_CTL_PUS_100K_UP (2 << 4)
		PAD_CTL_PUS_22K_UP (3 << 4)
		PAD_CTL_ODE_CMOS (0 << 3)
		PAD_CTL_ODE_OPENDRAIN (1 << 3)
		PAD_CTL_DSE_NOMINAL (0 << 1)
		PAD_CTL_DSE_HIGH (1 << 1)
		PAD_CTL_DSE_MAX (2 << 1)
		PAD_CTL_SRE_FAST (1 << 0)
		PAD_CTL_SRE_SLOW (0 << 0)

		Refer to imx25-pinfunc.h in device tree source folder for all available
		imx25 PIN_FUNC_ID.

Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt

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Original line number	Diff line number	Diff line
		@@ -52,12 +52,25 @@ Required properties for pin configuration node:
		CONFIG can be 0 or 1, meaning Pullup disable/enable.


		The iomux controller has gpio child nodes which are embedded in the iomux
		control registers. They have to be defined as child nodes of the iomux device
		node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
		properties for the iomux device node are required.

		Example:

		iomuxc: iomuxc@10015000 {
		compatible = "fsl,imx27-iomuxc";
		reg = <0x10015000 0x600>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio1: gpio@10015000 {
		...
		};

		...

		uart {
		pinctrl_uart1: uart-1 {
		@@ -83,6 +96,15 @@ The above example using macros:
		iomuxc: iomuxc@10015000 {
		compatible = "fsl,imx27-iomuxc";
		reg = <0x10015000 0x600>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio1: gpio@10015000 {
		...
		};

		...

		uart {
		pinctrl_uart1: uart-1 {

Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt

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		NVIDIA Tegra124 pinmux controller

		The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30
		pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
		nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
		a baseline, and only documents the differences between the two bindings.

		Required properties:
		- compatible: "nvidia,tegra124-pinmux"
		- reg: Should contain a list of base address and size pairs for:
		-- first entry - the drive strength and pad control registers.
		-- second entry - the pinmux registers

		Tegra124 adds the following optional properties for pin configuration subnodes.
		The macros for options are defined in the
		include/dt-binding/pinctrl/pinctrl-tegra.h.
		- nvidia,enable-input: Integer. Enable the pin's input path.
		enable :TEGRA_PIN_ENABLE0 and
		disable or output only: TEGRA_PIN_DISABLE.
		- nvidia,open-drain: Integer.
		enable: TEGRA_PIN_ENABLE.
		disable: TEGRA_PIN_DISABLE.
		- nvidia,lock: Integer. Lock the pin configuration against further changes
		until reset.
		enable: TEGRA_PIN_ENABLE.
		disable: TEGRA_PIN_DISABLE.
		- nvidia,io-reset: Integer. Reset the IO path.
		enable: TEGRA_PIN_ENABLE.
		disable: TEGRA_PIN_DISABLE.
		- nvidia,rcv-sel: Integer. Select VIL/VIH receivers.
		normal: TEGRA_PIN_DISABLE
		high: TEGRA_PIN_ENABLE

		Please refer the Tegra TRM for complete details regarding which groups
		support which functionality.

		Valid values for pin and group names are:

		per-pin mux groups:

		These all support nvidia,function, nvidia,tristate, nvidia,pull,
		nvidia,enable-input. Some support nvidia,lock nvidia,open-drain,
		nvidia,io-reset and nvidia,rcv-sel.

		ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
		ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
		ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
		dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
		sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
		sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
		ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
		uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
		uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_scl_pc4,
		gen1_i2c_sda_pc5, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6,
		dap4_sclk_pp7, clk3_out_pee0, clk3_req_pee1, pc7, pi5, pi7, pk0, pk1,
		pj0, pj2, pk3, pk4, pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6,
		pg7, ph0, ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
		pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, sdmmc4_clk_pcc4,
		sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, sdmmc4_dat2_paa2,
		sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
		sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, cam_i2c_scl_pbb1,
		cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, pcc2, jtag_rtck,
		pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
		kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
		kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
		kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, kb_col0_pq0, kb_col1_pq1,
		kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, kb_col6_pq6,
		kb_col7_pq7, clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n,
		clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
		dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, spdif_in_pk6,
		spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3,
		dvfs_pwm_px0, gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
		gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7,
		sdmmc3_clk_pa6, sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6,
		sdmmc3_dat2_pb5, sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1,
		pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3, pex_l1_rst_n_pdd5,
		pex_l1_clkreq_n_pdd6, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
		sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4,
		usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, sdmmc3_clk_lb_in_pee5,
		gmi_clk_lb, reset_out_n, kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1,
		pff2, dp_hpd_pff0,

		drive groups:

		These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
		nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
		support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
		and nvidia,drive-type.

		ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
		dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
		gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.

		Valid values for nvidia,functions are:

		blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
		displaya_alt, displayb, dtv, extperiph1, extperiph2, extperiph3,
		gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0,
		i2s1, i2s2, i2s3, i2s4, irda, kbc, owr, pmi, pwm0, pwm1, pwm2, pwm3,
		pwron, reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3,
		sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
		uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
		vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
		dp, rtck, sys, clk tmds.

		Example:

		pinmux: pinmux {
		compatible = "nvidia,tegra124-pinmux";
		reg = <0x70000868 0x164 /* Pad control registers */
		0x70003000 0x434>; /* PinMux registers */
		};

		Example pinmux entries:

		pinctrl {
		sdmmc4_default: pinmux {
		sdmmc4_clk_pcc4 {
		nvidia,pins = "sdmmc4_clk_pcc4",
		nvidia,function = "sdmmc4";
		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
		nvidia,tristate = <TEGRA_PIN_DISABLE>;
		};

		sdmmc4_dat0_paa0 {
		nvidia,pins = "sdmmc4_dat0_paa0",
		"sdmmc4_dat1_paa1",
		"sdmmc4_dat2_paa2",
		"sdmmc4_dat3_paa3",
		"sdmmc4_dat4_paa4",
		"sdmmc4_dat5_paa5",
		"sdmmc4_dat6_paa6",
		"sdmmc4_dat7_paa7";
		nvidia,function = "sdmmc4";
		nvidia,pull = <TEGRA_PIN_PULL_UP>;
		nvidia,tristate = <TEGRA_PIN_DISABLE>;
		};
		};
		};

		sdhci@78000400 {
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc4_default>;
		};

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

+3 −0

Original line number	Diff line number	Diff line
		@@ -151,6 +151,8 @@ drive-push-pull - drive actively high and low
		drive-open-drain - drive with open drain
		drive-open-source - drive with open source
		drive-strength - sink or source at most X mA
		input-enable - enable input on pin (no effect on output)
		input-disable - disable input on pin (no effect on output)
		input-schmitt-enable - enable schmitt-trigger mode
		input-schmitt-disable - disable schmitt-trigger mode
		input-debounce - debounce mode with debound time X
		@@ -158,6 +160,7 @@ low-power-enable - enable low power mode
		low-power-disable - disable low power mode
		output-low - set the pin to output mode with low level
		output-high - set the pin to output mode with high level
		slew-rate - set the slew rate

		Some of the generic properties take arguments. For those that do, the
		arguments are described below.

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