Commit a5325089 authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64: Handle erratum 1418040 as a superset of erratum 1188873 



We already mitigate erratum 1188873 affecting Cortex-A76 and
Neoverse-N1 r0p0 to r2p0. It turns out that revisions r0p0 to
r3p1 of the same cores are affected by erratum 1418040, which
has the same workaround as 1188873.

Let's expand the range of affected revisions to match 1418040,
and repaint all occurences of 1188873 to 1418040. Whilst we're
there, do a bit of reformating in silicon-errata.txt and drop
a now unnecessary dependency on ARM_ARCH_TIMER_OOL_WORKAROUND.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 1cf24a2c

Documentation/arm64/silicon-errata.txt

+4 −4
Original line number Diff line number Diff line
@@ -58,14 +58,14 @@ stable kernels. 
| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | Cortex-A76      | #1188873,1418040| ARM64_ERRATUM_1418040       |

| ARM            | Cortex-A76      | #1165522        | ARM64_ERRATUM_1165522       |

| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |

| ARM            | Neoverse-N1     | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

| ARM            | MMU-500         | #841119,826419  | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

| Cavium         | ThunderX ITS    | #22375,24313    | CAVIUM_ERRATUM_22375        |

| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144        |

| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |

| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |

arch/arm64/Kconfig

+3 −4
Original line number Diff line number Diff line
@@ -475,16 +475,15 @@ config ARM64_ERRATUM_1024718 


	  If unsure, say Y.



config ARM64_ERRATUM_1188873

config ARM64_ERRATUM_1418040

	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"

	default y

	depends on COMPAT

	select ARM_ARCH_TIMER_OOL_WORKAROUND

	help

	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1

	  erratum 1188873.

	  errata 1188873 and 1418040.



	  Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could

	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could

	  cause register corruption when accessing the timer registers

	  from AArch32 userspace.

arch/arm64/include/asm/cpucaps.h

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 
#define ARM64_HAS_STAGE2_FWB			32

#define ARM64_HAS_CRC32				33

#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1188873		35

#define ARM64_WORKAROUND_1418040		35

#define ARM64_HAS_SB				36

#define ARM64_WORKAROUND_1165522		37

#define ARM64_HAS_ADDRESS_AUTH_ARCH		38

arch/arm64/kernel/cpu_errata.c

+14 −10
Original line number Diff line number Diff line
@@ -698,12 +698,16 @@ static const struct midr_range workaround_clean_cache[] = { 
};

#endif



#ifdef CONFIG_ARM64_ERRATUM_1188873

static const struct midr_range erratum_1188873_list[] = {

	/* Cortex-A76 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),

	/* Neoverse-N1 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0),

#ifdef CONFIG_ARM64_ERRATUM_1418040

/*

 * - 1188873 affects r0p0 to r2p0

 * - 1418040 affects r0p0 to r3p1

 */

static const struct midr_range erratum_1418040_list[] = {

	/* Cortex-A76 r0p0 to r3p1 */

	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),

	/* Neoverse-N1 r0p0 to r3p1 */

	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),

	{},

};

#endif
@@ -825,11 +829,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.matches = has_ssbd_mitigation,

		.midr_range_list = arm64_ssb_cpus,

	},

#ifdef CONFIG_ARM64_ERRATUM_1188873

#ifdef CONFIG_ARM64_ERRATUM_1418040

	{

		.desc = "ARM erratum 1188873",

		.capability = ARM64_WORKAROUND_1188873,

		ERRATA_MIDR_RANGE_LIST(erratum_1188873_list),

		.desc = "ARM erratum 1418040",

		.capability = ARM64_WORKAROUND_1418040,

		ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1165522

arch/arm64/kernel/entry.S

+2 −2
Original line number Diff line number Diff line
@@ -336,8 +336,8 @@ alternative_if ARM64_WORKAROUND_845719 
alternative_else_nop_endif

#endif

3:

#ifdef CONFIG_ARM64_ERRATUM_1188873

alternative_if_not ARM64_WORKAROUND_1188873

#ifdef CONFIG_ARM64_ERRATUM_1418040

alternative_if_not ARM64_WORKAROUND_1418040

	b	4f

alternative_else_nop_endif

	/*

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