Unverified Commit a51acc24 authored by Damien Le Moal's avatar Damien Le Moal Committed by Mark Brown
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spi: dw: Add support for 32-bits max xfer size 



The Synopsis DesignWare DW_apb_ssi specifications version 3.23 onward
define a 32-bits maximum transfer size synthesis parameter
(SSI_MAX_XFER_SIZE=32) in addition to the legacy 16-bits configuration
(SSI_MAX_XFER_SIZE=16) for SPI controllers. When SSI_MAX_XFER_SIZE=32,
the layout of the ctrlr0 register changes, moving the data frame format
field from bits [3..0] to bits [16..20], and the RX/TX FIFO word size
can be up to 32-bits.

To support this new format, introduce the DW SPI capability flag
DW_SPI_CAP_DFS32 to indicate that a controller is configured with
SSI_MAX_XFER_SIZE=32. Since SSI_MAX_XFER_SIZE is a controller synthesis
parameter not accessible through a register, the detection of this
parameter value is done in spi_hw_init() by writing and reading the
ctrlr0 register and testing the value of bits [3..0]. These bits are
ignored (unchanged) for SSI_MAX_XFER_SIZE=16, allowing the detection.
If a DFS32 capable SPI controller is detected, the new field dfs_offset
in struct dw_spi is set to SPI_DFS32_OFFSET (16).

dw_spi_update_config() is modified to set the data frame size field at
the correct position is the CTRLR0 register, as indicated by the
dfs_offset field of the dw_spi structure.

The DW_SPI_CAP_DFS32 flag is also unconditionally set for SPI slave
controllers, e.g. controllers that have the DW_SPI_CAP_DWC_SSI
capability flag set. However, for these ssi controllers, the dfs_offset
field is set to 0 as before (as per specifications).

Finally, for any controller with the DW_SPI_CAP_DFS32 capability flag
set, dw_spi_add_host() extends the value of bits_per_word_mask from
16-bits to 32-bits. dw_reader() and dw_writer() are also modified to
handle 32-bits iTX/RX FIFO words.

Suggested-by: default avatarSean Anderson <seanga2@gmail.com>
Signed-off-by: default avatarDamien Le Moal <damien.lemoal@wdc.com>
Acked-by: default avatarSerge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20201206011817.11700-3-damien.lemoal@wdc.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7b14a272

drivers/spi/spi-dw-core.c

+37 −7
Original line number Diff line number Diff line
@@ -137,14 +137,16 @@ static inline u32 rx_max(struct dw_spi *dws) 
static void dw_writer(struct dw_spi *dws)

{

	u32 max = tx_max(dws);

	u16 txw = 0;

	u32 txw = 0;



	while (max--) {

		if (dws->tx) {

			if (dws->n_bytes == 1)

				txw = *(u8 *)(dws->tx);

			else

			else if (dws->n_bytes == 2)

				txw = *(u16 *)(dws->tx);

			else

				txw = *(u32 *)(dws->tx);



			dws->tx += dws->n_bytes;

		}
@@ -156,15 +158,17 @@ static void dw_writer(struct dw_spi *dws) 
static void dw_reader(struct dw_spi *dws)

{

	u32 max = rx_max(dws);

	u16 rxw;

	u32 rxw;



	while (max--) {

		rxw = dw_read_io_reg(dws, DW_SPI_DR);

		if (dws->rx) {

			if (dws->n_bytes == 1)

				*(u8 *)(dws->rx) = rxw;

			else

			else if (dws->n_bytes == 2)

				*(u16 *)(dws->rx) = rxw;

			else

				*(u32 *)(dws->rx) = rxw;



			dws->rx += dws->n_bytes;

		}
@@ -311,8 +315,8 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, 
	u32 speed_hz;

	u16 clk_div;



	/* CTRLR0[ 4/3: 0] Data Frame Size */

	cr0 |= (cfg->dfs - 1);

	/* CTRLR0[ 4/3: 0] or CTRLR0[ 20: 16] Data Frame Size */

	cr0 |= (cfg->dfs - 1) << dws->dfs_offset;



	if (!(dws->caps & DW_SPI_CAP_DWC_SSI))

		/* CTRLR0[ 9:8] Transfer Mode */
@@ -828,6 +832,29 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) 
		dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);

	}



	/*

	 * Detect CTRLR0.DFS field size and offset by testing the lowest bits

	 * writability. Note DWC SSI controller also has the extended DFS, but

	 * with zero offset.

	 */

	if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) {

		u32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0);



		spi_enable_chip(dws, 0);

		dw_writel(dws, DW_SPI_CTRLR0, 0xffffffff);

		cr0 = dw_readl(dws, DW_SPI_CTRLR0);

		dw_writel(dws, DW_SPI_CTRLR0, tmp);

		spi_enable_chip(dws, 1);



		if (!(cr0 & SPI_DFS_MASK)) {

			dws->caps |= DW_SPI_CAP_DFS32;

			dws->dfs_offset = SPI_DFS32_OFFSET;

			dev_dbg(dev, "Detected 32-bits max data frame size\n");

		}

	} else {

		dws->caps |= DW_SPI_CAP_DFS32;

	}



	/* enable HW fixup for explicit CS deselect for Amazon's alpine chip */

	if (dws->caps & DW_SPI_CAP_CS_OVERRIDE)

		dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
@@ -864,6 +891,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) 


	master->use_gpio_descriptors = true;

	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;

	if (dws->caps & DW_SPI_CAP_DFS32)

		master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);

	else

		master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);

	master->bus_num = dws->bus_num;

	master->num_chipselect = dws->num_cs;

drivers/spi/spi-dw.h

+5 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/io.h>

#include <linux/scatterlist.h>

#include <linux/spi/spi-mem.h>

#include <linux/bitfield.h>



/* Register offsets */

#define DW_SPI_CTRLR0			0x00
@@ -41,6 +42,8 @@ 


/* Bit fields in CTRLR0 */

#define SPI_DFS_OFFSET			0

#define SPI_DFS_MASK			GENMASK(3, 0)

#define SPI_DFS32_OFFSET		16



#define SPI_FRF_OFFSET			4

#define SPI_FRF_SPI			0x0
@@ -121,6 +124,7 @@ enum dw_ssi_type { 
#define DW_SPI_CAP_CS_OVERRIDE		BIT(0)

#define DW_SPI_CAP_KEEMBAY_MST		BIT(1)

#define DW_SPI_CAP_DWC_SSI		BIT(2)

#define DW_SPI_CAP_DFS32		BIT(3)



/* Slave spi_transfer/spi_mem_op related */

struct dw_spi_cfg {
@@ -148,6 +152,7 @@ struct dw_spi { 
	unsigned long		paddr;

	int			irq;

	u32			fifo_len;	/* depth of the FIFO buffer */

	unsigned int		dfs_offset;     /* CTRLR0 DFS field offset */

	u32			max_mem_freq;	/* max mem-ops bus freq */

	u32			max_freq;	/* max bus freq supported */

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