Commit a4ee7bac authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC updates from Vineet Gupta:

 - Intc imporvements [Yuriy]

 - VDK platform updates [Alexey]

* tag 'arc-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant
  ARCv2: intc: Delete useless comments in Device Trees
  ARCv2: IDU-intc: Delete deprecated parameters in Device Trees
  ARCv2: IDU-intc: mask all common interrupts by default
  ARCv2: IDU-intc: Use build registers for getting numbers of interrupts
  ARCv2: intc: Set default priority for all core interrupts
  ARCv2: intc: Use runtime value of irq count for setting up intc
  ARCv2: intc: Rework the build time irq count information
  ARC: [intc-*]: confine NR_CPU_IRQS to intc code
  ARCv2: intc: Use ARC_REG_STATUS32 for addressing STATUS32 reg
  arc: vdk: Add support of UIO
  arc: vdk: Add support of MMC controller
  arc: vdk: Disable halt on reset
parents 38705613 8ba605b6

Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt

+6 −18
Original line number Diff line number Diff line
@@ -8,15 +8,11 @@ Properties: 
- compatible: "snps,archs-idu-intc"

- interrupt-controller: This is an interrupt controller.

- interrupt-parent: <reference to parent core intc>

- #interrupt-cells: Must be <2>.

- interrupts: <...> specifies the upstream core irqs

- #interrupt-cells: Must be <1>.



  First cell specifies the "common" IRQ from peripheral to IDU

  Second cell specifies the irq distribution mode to cores

     0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3



  The second cell in interrupts property is deprecated and may be ignored by

  the kernel.

  Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N

  of the particular interrupt line of IDU corresponds to the line N+24 of the

  core interrupt controller.



  intc accessed via the special ARC AUX register interface, hence "reg" property

  is not specified.
@@ -32,18 +28,10 @@ Example: 
		compatible = "snps,archs-idu-intc";

		interrupt-controller;

		interrupt-parent = <&core_intc>;



		/*

		 * <hwirq  distribution>

		 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

		 */

		#interrupt-cells = <2>;



		/* upstream core irqs: downstream these are "COMMON" irq 0,1..  */

		interrupts = <24 25 26 27 28 29 30 31>;

		#interrupt-cells = <1>;

	};



	some_device: serial@c0fc1000 {

		interrupt-parent = <&idu_intc>;

		interrupts = <0 0>;	/* upstream idu IRQ #24, Round Robin */

		interrupts = <0>;	/* upstream idu IRQ #24 */

	};

arch/arc/Kconfig

+0 −17
Original line number Diff line number Diff line
@@ -180,16 +180,12 @@ config CPU_BIG_ENDIAN 
config SMP

	bool "Symmetric Multi-Processing"

	default n

	select ARC_HAS_COH_CACHES if ISA_ARCV2

	select ARC_MCIP if ISA_ARCV2

	help

	  This enables support for systems with more than one CPU.



if SMP



config ARC_HAS_COH_CACHES

	def_bool n



config NR_CPUS

	int "Maximum number of CPUs (2-4096)"

	range 2 4096
@@ -219,8 +215,6 @@ config ARC_MCIP 
menuconfig ARC_CACHE

	bool "Enable Cache Support"

	default y

	# if SMP, cache enabled ONLY if ARC implementation has cache coherency

	depends on !SMP || ARC_HAS_COH_CACHES



if ARC_CACHE
@@ -412,17 +406,6 @@ config ARC_HAS_DIV_REM 
	bool "Insn: div, divu, rem, remu"

	default y



config ARC_NUMBER_OF_INTERRUPTS

	int "Number of interrupts"

	range 8 240

	default 32

	help

	  This defines the number of interrupts on the ARCv2HS core.

	  It affects the size of vector table.

	  The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable

	  in hardware, it keep things simple for Linux to assume they are always

	  present.



endif	# ISA_ARCV2



endmenu   # "ARC CPU Configuration"

arch/arc/boot/dts/axc003_idu.dtsi

+3 −20
Original line number Diff line number Diff line
@@ -40,18 +40,7 @@ 
			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;



			/*

			 * <hwirq  distribution>

			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

			 */

			#interrupt-cells = <2>;



			/*

			 * upstream irqs to core intc - downstream these are

			 * "COMMON" irq 0,1..

			 */

			interrupts = <24 25>;

			#interrupt-cells = <1>;

		};



		/*
@@ -73,12 +62,7 @@ 
				interrupt-controller;

				#interrupt-cells = <2>;

				interrupt-parent = <&idu_intc>;



				/*

				 * cmn irq 1 -> cpu irq 25

				 * Distribute to cpu0 only

				 */

				interrupts = <1 1>;

				interrupts = <1>;

			};

		};
@@ -119,8 +103,7 @@ 
		reg = < 0xe0012000 0x200 >;

		interrupt-controller;

		interrupt-parent = <&idu_intc>;

		interrupts = <0 1>;	/* cmn irq 0 -> cpu irq 24

					   distribute to cpu0 only */

		interrupts = <0>;

	};



	memory {

arch/arc/boot/dts/haps_hs_idu.dts

+2 −9
Original line number Diff line number Diff line
@@ -47,18 +47,13 @@ 
			compatible = "snps,archs-intc";

			interrupt-controller;

			#interrupt-cells = <1>;

/*			interrupts = <16 17 18 19 20 21 22 23 24 25>; */

		};



		idu_intc: idu-interrupt-controller {

			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;

			/* <hwirq  distribution>

			distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */

			#interrupt-cells = <2>;

			interrupts = <24 25 26 27 28 29 30 31>;



			#interrupt-cells = <1>;

		};



		uart0: serial@f0000000 {
@@ -66,9 +61,7 @@ 
			compatible = "ns16550a";

			reg = <0xf0000000 0x2000>;

			interrupt-parent = <&idu_intc>;

			/* interrupts = <0 1>;  DEST=1*/

			/* interrupts = <0 2>;  DEST=2*/

			interrupts = <0 0>;  /* RR*/

			interrupts = <0>;

			clock-frequency = <50000000>;

			baud = <115200>;

			reg-shift = <2>;

arch/arc/boot/dts/nsim_hs_idu.dts

+2 −13
Original line number Diff line number Diff line
@@ -46,25 +46,14 @@ 
			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;



			/*

			 * <hwirq  distribution>

			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

			 */

			#interrupt-cells = <2>;



			/*

			 * upstream irqs to core intc - downstream these are

			 * "COMMON" irq 0,1..

			 */

			interrupts = <24 25 26 27 28 29 30 31>;

			#interrupt-cells = <1>;

		};



		arcuart0: serial@c0fc1000 {

			compatible = "snps,arc-uart";

			reg = <0xc0fc1000 0x100>;

			interrupt-parent = <&idu_intc>;

			interrupts = <0 0>;

			interrupts = <0>;

			clock-frequency = <80000000>;

			current-speed = <115200>;

			status = "okay";

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