powerpc/e6500: Update machine check for L1D cache err (a4e89ffb) · Commits · 戴 / test

This patch updates the machine check handler of Linux kernel to handle the e6500 architecture case. In e6500 core, L1 Data Cache Write Shadow Mode (DCWS) register is not implemented but L1 data cache always runs in write shadow mode. So, on L1 data cache parity errors, hardware will automatically invalidate the data cache but will still log a machine check interrupt. Signed-off-by:

Ronak Desai <ronak.desai@rockwellcollins.com> Signed-off-by:

Matthew Weber <matthew.weber@rockwellcollins.com> Signed-off-by:

Scott Wood <oss@buserror.net>

arch/powerpc/kernel/traps.c

+10 −2

Original line number	Diff line number	Diff line
		@@ -393,6 +393,7 @@ static inline int check_io_access(struct pt_regs *regs)
		int machine_check_e500mc(struct pt_regs *regs)
		{
		unsigned long mcsr = mfspr(SPRN_MCSR);
		unsigned long pvr = mfspr(SPRN_PVR);
		unsigned long reason = mcsr;
		int recoverable = 1;

		@@ -434,9 +435,16 @@ int machine_check_e500mc(struct pt_regs *regs)
		* may still get logged and cause a machine check. We should
		* only treat the non-write shadow case as non-recoverable.
		*/
		/* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
		* is not implemented but L1 data cache always runs in write
		* shadow mode. Hence on data cache parity errors HW will
		* automatically invalidate the L1 Data Cache.
		*/
		if (PVR_VER(pvr) != PVR_VER_E6500) {
		if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
		recoverable = 0;
		}
		}

		if (reason & MCSR_L2MMU_MHIT) {
		printk("Hit on multiple TLB entries\n");

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