Commit a4dfccf8 authored by Sascha Hauer's avatar Sascha Hauer
Browse files

ARM i.MX51: setup MIPI during startup 



The MIPI interface has to be initialized for proper IPU support.
The MIPI officially is not supported, but still needs initialization.
This patch adds this to the SoC startup as all it does is poking
some magic values into registers for which we do not have documentation.

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 376aaac1

arch/arm/mach-imx/mm-imx5.c

+20 −0
Original line number Diff line number Diff line
@@ -81,8 +81,28 @@ void __init imx50_init_early(void) 
	mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));

}



/*

 * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by

 * the Freescale marketing division. However this did not remove the

 * hardware from the chip which still needs to be configured for proper

 * IPU support.

 */

static void __init imx51_ipu_mipi_setup(void)

{

	void __iomem *hsc_addr;

	hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);



	/* setup MIPI module to legacy mode */

	__raw_writel(0xf00, hsc_addr);



	/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */

	__raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,

		hsc_addr + 0x800);

}



void __init imx51_init_early(void)

{

	imx51_ipu_mipi_setup();

	mxc_set_cpu_type(MXC_CPU_MX51);

	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));

	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));

CRA Git | Maintained and supported by SUSTech CRA and CCSE