Commit a4dbbcee authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Boyd
Browse files

clk: tegra: Fixes for MBIST work around 



Fix some incorrect data in LVL2 offset and bit mask.

Fixes: e403d005 ("clk: tegra: MBIST work around for Tegra210")
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 923ca132

drivers/clk/tegra/clk-tegra210.c

+3 −3
Original line number Diff line number Diff line
@@ -2603,7 +2603,7 @@ static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = { 
	[TEGRA_POWERGATE_MPE] = {

		.handle_lvl2_ovr = tegra210_generic_mbist_war,

		.lvl2_offset = LVL2_CLK_GATE_OVRE,

		.lvl2_mask = BIT(2),

		.lvl2_mask = BIT(29),

	},

	[TEGRA_POWERGATE_SOR] = {

		.handle_lvl2_ovr = tegra210_generic_mbist_war,
@@ -2654,14 +2654,14 @@ static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = { 
		.num_clks = ARRAY_SIZE(nvdec_slcg_clkids),

		.clk_init_data = nvdec_slcg_clkids,

		.handle_lvl2_ovr = tegra210_generic_mbist_war,

		.lvl2_offset = LVL2_CLK_GATE_OVRC,

		.lvl2_offset = LVL2_CLK_GATE_OVRE,

		.lvl2_mask = BIT(9) | BIT(31),

	},

	[TEGRA_POWERGATE_NVJPG] = {

		.num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),

		.clk_init_data = nvjpg_slcg_clkids,

		.handle_lvl2_ovr = tegra210_generic_mbist_war,

		.lvl2_offset = LVL2_CLK_GATE_OVRC,

		.lvl2_offset = LVL2_CLK_GATE_OVRE,

		.lvl2_mask = BIT(9) | BIT(31),

	},

	[TEGRA_POWERGATE_AUD] = {

CRA Git | Maintained and supported by SUSTech CRA and CCSE