Commit a4c31557 authored by Jack Steiner's avatar Jack Steiner Committed by Linus Torvalds
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sgi-gru: add definitions of x86_64 GRU MMRs 



Add definitions for x86_64 GRU MMRs.

Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent bc5d9940

arch/x86/include/asm/uv/uv_mmrs.h

+153 −0
Original line number Diff line number Diff line 


/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive
@@ -242,6 +243,158 @@ union uvh_event_occurred0_u { 
#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL

#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0



/* ========================================================================= */

/*                         UVH_GR0_TLB_INT0_CONFIG                           */

/* ========================================================================= */

#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL



#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0

#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL

#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8

#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL

#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11

#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL

#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12

#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL

#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13

#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL

#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15

#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL

#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16

#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL

#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32

#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL



union uvh_gr0_tlb_int0_config_u {

    unsigned long	v;

    struct uvh_gr0_tlb_int0_config_s {

	unsigned long	vector_  :  8;  /* RW */

	unsigned long	dm       :  3;  /* RW */

	unsigned long	destmode :  1;  /* RW */

	unsigned long	status   :  1;  /* RO */

	unsigned long	p        :  1;  /* RO */

	unsigned long	rsvd_14  :  1;  /*    */

	unsigned long	t        :  1;  /* RO */

	unsigned long	m        :  1;  /* RW */

	unsigned long	rsvd_17_31: 15;  /*    */

	unsigned long	apic_id  : 32;  /* RW */

    } s;

};



/* ========================================================================= */

/*                         UVH_GR0_TLB_INT1_CONFIG                           */

/* ========================================================================= */

#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL



#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0

#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL

#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8

#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL

#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11

#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL

#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12

#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL

#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13

#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL

#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15

#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL

#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16

#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL

#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32

#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL



union uvh_gr0_tlb_int1_config_u {

    unsigned long	v;

    struct uvh_gr0_tlb_int1_config_s {

	unsigned long	vector_  :  8;  /* RW */

	unsigned long	dm       :  3;  /* RW */

	unsigned long	destmode :  1;  /* RW */

	unsigned long	status   :  1;  /* RO */

	unsigned long	p        :  1;  /* RO */

	unsigned long	rsvd_14  :  1;  /*    */

	unsigned long	t        :  1;  /* RO */

	unsigned long	m        :  1;  /* RW */

	unsigned long	rsvd_17_31: 15;  /*    */

	unsigned long	apic_id  : 32;  /* RW */

    } s;

};



/* ========================================================================= */

/*                         UVH_GR1_TLB_INT0_CONFIG                           */

/* ========================================================================= */

#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL



#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0

#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL

#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8

#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL

#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11

#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL

#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12

#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL

#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13

#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL

#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15

#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL

#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16

#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL

#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32

#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL



union uvh_gr1_tlb_int0_config_u {

    unsigned long	v;

    struct uvh_gr1_tlb_int0_config_s {

	unsigned long	vector_  :  8;  /* RW */

	unsigned long	dm       :  3;  /* RW */

	unsigned long	destmode :  1;  /* RW */

	unsigned long	status   :  1;  /* RO */

	unsigned long	p        :  1;  /* RO */

	unsigned long	rsvd_14  :  1;  /*    */

	unsigned long	t        :  1;  /* RO */

	unsigned long	m        :  1;  /* RW */

	unsigned long	rsvd_17_31: 15;  /*    */

	unsigned long	apic_id  : 32;  /* RW */

    } s;

};



/* ========================================================================= */

/*                         UVH_GR1_TLB_INT1_CONFIG                           */

/* ========================================================================= */

#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL



#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0

#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL

#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8

#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL

#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11

#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL

#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12

#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL

#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13

#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL

#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15

#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL

#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16

#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL

#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32

#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL



union uvh_gr1_tlb_int1_config_u {

    unsigned long	v;

    struct uvh_gr1_tlb_int1_config_s {

	unsigned long	vector_  :  8;  /* RW */

	unsigned long	dm       :  3;  /* RW */

	unsigned long	destmode :  1;  /* RW */

	unsigned long	status   :  1;  /* RO */

	unsigned long	p        :  1;  /* RO */

	unsigned long	rsvd_14  :  1;  /*    */

	unsigned long	t        :  1;  /* RO */

	unsigned long	m        :  1;  /* RW */

	unsigned long	rsvd_17_31: 15;  /*    */

	unsigned long	apic_id  : 32;  /* RW */

    } s;

};



/* ========================================================================= */

/*                               UVH_INT_CMPB                                */

/* ========================================================================= */

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