Commit a4ac7693 authored by Jiange Zhao's avatar Jiange Zhao Committed by Alex Deucher
Browse files

drm/amdgpu/SRIOV: Navi10/12 VF doesn't support SMU 



In SRIOV case, SMU and powerplay are handled in HV.

VF shouldn't have control over SMU and powerplay.

Signed-off-by: default avatarJiange Zhao <Jiange.Zhao@amd.com>
Reviewed-by: default avatarEmily Deng <Emily.Deng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a90a24d5

drivers/gpu/drm/amd/amdgpu/nv.c

+4 −4
Original line number Diff line number Diff line
@@ -439,7 +439,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&

		    is_support_sw_smu(adev))

		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -450,7 +450,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    is_support_sw_smu(adev))

		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		if (adev->enable_mes)
@@ -462,7 +462,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&

		    is_support_sw_smu(adev))

		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -473,7 +473,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    is_support_sw_smu(adev))

		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		break;

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