Commit a49a9dcc authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-09-07' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Seems to have been overly quiet this week so I expect next week will
  be more stuff, just one pull from Rodrigo with i915 fixes in it.

  Quoting Rodrigo:

    'The critical fix here on display side is the DP MST regression one.

     But this pull also include fixes for DP SST, small VDSC register
     fix and GVT's bucked with "BXT fixes, two guest warning fixes,
     dmabuf format mod fix and one for recent multiple VM timeout
     failure'."

* tag 'drm-fixes-2018-09-07' of git://anongit.freedesktop.org/drm/drm:
  drm/i915/dp_mst: Fix enabling pipe clock for all streams
  drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
  drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
  drm/i915/gvt: Give new born vGPU higher scheduling chance
  drm/i915/gvt: Fix drm_format_mod value for vGPU plane
  drm/i915/gvt: move intel_runtime_pm_get out of spin_lock in stop_schedule
  drm/i915/gvt: Handle GEN9_WM_CHICKEN3 with F_CMD_ACCESS.
  drm/i915/gvt: Make correct handling to vreg BXT_PHY_CTL_FAMILY
  drm/i915/gvt: emulate gen9 dbuf ctl register access
parents 631267f6 67c6ed7c

drivers/gpu/drm/i915/gvt/dmabuf.c

+26 −7
Original line number Diff line number Diff line
@@ -170,20 +170,22 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 
		unsigned int tiling_mode = 0;

		unsigned int stride = 0;



		switch (info->drm_format_mod << 10) {

		case PLANE_CTL_TILED_LINEAR:

		switch (info->drm_format_mod) {

		case DRM_FORMAT_MOD_LINEAR:

			tiling_mode = I915_TILING_NONE;

			break;

		case PLANE_CTL_TILED_X:

		case I915_FORMAT_MOD_X_TILED:

			tiling_mode = I915_TILING_X;

			stride = info->stride;

			break;

		case PLANE_CTL_TILED_Y:

		case I915_FORMAT_MOD_Y_TILED:

		case I915_FORMAT_MOD_Yf_TILED:

			tiling_mode = I915_TILING_Y;

			stride = info->stride;

			break;

		default:

			gvt_dbg_core("not supported tiling mode\n");

			gvt_dbg_core("invalid drm_format_mod %llx for tiling\n",

				     info->drm_format_mod);

		}

		obj->tiling_and_stride = tiling_mode | stride;

	} else {
@@ -222,7 +224,24 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
		info->height = p.height;

		info->stride = p.stride;

		info->drm_format = p.drm_format;

		info->drm_format_mod = p.tiled;



		switch (p.tiled) {

		case PLANE_CTL_TILED_LINEAR:

			info->drm_format_mod = DRM_FORMAT_MOD_LINEAR;

			break;

		case PLANE_CTL_TILED_X:

			info->drm_format_mod = I915_FORMAT_MOD_X_TILED;

			break;

		case PLANE_CTL_TILED_Y:

			info->drm_format_mod = I915_FORMAT_MOD_Y_TILED;

			break;

		case PLANE_CTL_TILED_YF:

			info->drm_format_mod = I915_FORMAT_MOD_Yf_TILED;

			break;

		default:

			gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);

		}



		info->size = (((p.stride * p.height * p.bpp) / 8) +

			      (PAGE_SIZE - 1)) >> PAGE_SHIFT;

	} else if (plane_id == DRM_PLANE_TYPE_CURSOR) {

drivers/gpu/drm/i915/gvt/fb_decoder.c

+2 −3
Original line number Diff line number Diff line
@@ -220,8 +220,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

		plane->tiled = (val & PLANE_CTL_TILED_MASK) >>

		_PLANE_CTL_TILED_SHIFT;

		plane->tiled = val & PLANE_CTL_TILED_MASK;

		fmt = skl_format_to_drm(

			val & PLANE_CTL_FORMAT_MASK,

			val & PLANE_CTL_ORDER_RGBX,
@@ -260,7 +259,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
		return  -EINVAL;

	}



	plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),

	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,

		(IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) ?

drivers/gpu/drm/i915/gvt/fb_decoder.h

+1 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ struct intel_gvt; 
/* color space conversion and gamma correction are not included */

struct intel_vgpu_primary_plane_format {

	u8	enabled;	/* plane is enabled */

	u8	tiled;		/* X-tiled */

	u32	tiled;		/* tiling mode: linear, X-tiled, Y tiled, etc */

	u8	bpp;		/* bits per pixel */

	u32	hw_format;	/* format field in the PRI_CTL register */

	u32	drm_format;	/* format in DRM definition */

drivers/gpu/drm/i915/gvt/handlers.c

+27 −6
Original line number Diff line number Diff line
@@ -1296,6 +1296,19 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 
	return 0;

}



static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)

{

	write_vreg(vgpu, offset, p_data, bytes);



	if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)

		vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;

	else

		vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;



	return 0;

}



static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,

	unsigned int offset, void *p_data, unsigned int bytes)

{
@@ -1525,9 +1538,15 @@ static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 
	u32 v = *(u32 *)p_data;

	u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;



	switch (offset) {

	case _PHY_CTL_FAMILY_EDP:

		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;

		break;

	case _PHY_CTL_FAMILY_DDI:

		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;

		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;

		break;

	}



	vgpu_vreg(vgpu, offset) = v;
@@ -2812,6 +2831,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
	MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,

		skl_power_well_ctl_write);



	MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);



	MMIO_D(_MMIO(0xa210), D_SKL_PLUS);

	MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);

	MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
@@ -2987,8 +3008,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
		NULL, gen9_trtte_write);

	MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);



	MMIO_D(_MMIO(0x45008), D_SKL_PLUS);



	MMIO_D(_MMIO(0x46430), D_SKL_PLUS);



	MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
@@ -3026,6 +3045,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
	MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,

		 NULL, NULL);

	MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,

		 NULL, NULL);



	MMIO_D(_MMIO(0x4ab8), D_KBL);

	MMIO_D(_MMIO(0x2248), D_KBL | D_SKL);

drivers/gpu/drm/i915/gvt/mmio_context.c

+0 −2
Original line number Diff line number Diff line
@@ -562,11 +562,9 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre, 
	 * performace for batch mmio read/write, so we need

	 * handle forcewake mannually.

	 */

	intel_runtime_pm_get(dev_priv);

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

	switch_mmio(pre, next, ring_id);

	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	intel_runtime_pm_put(dev_priv);

}



/**

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