Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal (a455eda3) · Commits · 戴 / test

Documentation/devicetree/bindings/thermal/amazon,al-thermal.txt

0 → 100644

+33 −0

Original line number	Diff line number	Diff line
		Amazon's Annapurna Labs Thermal Sensor

		Simple thermal device that allows temperature reading by a single MMIO
		transaction.

		Required properties:
		- compatible: "amazon,al-thermal".
		- reg: The physical base address and length of the sensor's registers.
		- #thermal-sensor-cells: Must be 1. See ./thermal.txt for a description.

		Example:
		thermal: thermal {
		compatible = "amazon,al-thermal";
		reg = <0x0 0x05002860 0x0 0x1>;
		#thermal-sensor-cells = <0x1>;
		};

		thermal-zones {
		thermal-z0 {
		polling-delay-passive = <250>;
		polling-delay = <1000>;
		thermal-sensors = <&thermal 0>;
		trips {
		critical {
		temperature = <105000>;
		hysteresis = <2000>;
		type = "critical";
		};
		};

		};
		};

Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt

+57 −5

Original line number	Diff line number	Diff line
		@@ -52,13 +52,47 @@ Required properties :
		Must set as following values:
		TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
		TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
		- nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210.
		It is the level of pulse skippers, which used to throttle clock
		frequencies. It indicates gpu clock throttling depth and can be
		programmed to any of the following values which represent a throttling
		percentage:
		TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
		TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%),
		TEGRA_SOCTHERM_THROT_LEVEL_MED (75%),
		TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%).
		- #cooling-cells: Should be 1. This cooling device only support on/off state.
		See ./thermal.txt for a description of this property.

		Optional properties: The following properties are T210 specific and
		valid only for OCx throttle events.
		- nvidia,count-threshold: Specifies the number of OC events that are
		required for triggering an interrupt. Interrupts are not triggered if
		the property is missing. A value of 0 will interrupt on every OC alarm.
		- nvidia,polarity-active-low: Configures the polarity of the OC alaram
		signal. If present, this means assert low, otherwise assert high.
		- nvidia,alarm-filter: Number of clocks to filter event. When the filter
		expires (which means the OC event has not occurred for a long time),
		the counter is cleared and filter is rearmed. Default value is 0.
		- nvidia,throttle-period-us: Specifies the number of uSec for which
		throttling is engaged after the OC event is deasserted. Default value
		is 0.

		Optional properties:
		- nvidia,thermtrips : When present, this property specifies the temperature at
		which the soctherm hardware will assert the thermal trigger signal to the
		Power Management IC, which can be configured to reset or shutdown the device.
		It is an array of pairs where each pair represents a tsensor id followed by a
		temperature in milli Celcius. In the absence of this property the critical
		trip point will be used for thermtrip temperature.

		Note:
		- the "critical" type trip points will be set to SOC_THERM hardware as the
		shut down temperature. Once the temperature of this thermal zone is higher
		than it, the system will be shutdown or reset by hardware.
		- the "critical" type trip points will be used to set the temperature at which
		the SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips"
		property is missing. When the thermtrips property is present, the breach of a
		critical trip point is reported back to the thermal framework to implement
		software shutdown.

		- the "hot" type trip points will be set to SOC_THERM hardware as the throttle
		temperature. Once the the temperature of this thermal zone is higher
		than it, it will trigger the HW throttle event.
		@@ -79,25 +113,32 @@ Example :

		#thermal-sensor-cells = <1>;

		nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
		TEGRA124_SOCTHERM_SENSOR_GPU 103000>;

		throttle-cfgs {
		/*
		* When the "heavy" cooling device triggered,
		* the HW will skip cpu clock's pulse in 85% depth
		* the HW will skip cpu clock's pulse in 85% depth,
		* skip gpu clock's pulse in 85% level
		*/
		throttle_heavy: heavy {
		nvidia,priority = <100>;
		nvidia,cpu-throt-percent = <85>;
		nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;

		#cooling-cells = <1>;
		};

		/*
		* When the "light" cooling device triggered,
		* the HW will skip cpu clock's pulse in 50% depth
		* the HW will skip cpu clock's pulse in 50% depth,
		* skip gpu clock's pulse in 50% level
		*/
		throttle_light: light {
		nvidia,priority = <80>;
		nvidia,cpu-throt-percent = <50>;
		nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;

		#cooling-cells = <1>;
		};
		@@ -107,6 +148,17 @@ Example :
		* arbiter will select the highest priority as the final throttle
		* settings to skip cpu pulse.
		*/

		throttle_oc1: oc1 {
		nvidia,priority = <50>;
		nvidia,polarity-active-low;
		nvidia,count-threshold = <100>;
		nvidia,alarm-filter = <5100000>;
		nvidia,throttle-period-us = <0>;
		nvidia,cpu-throt-percent = <75>;
		nvidia,gpu-throt-level =
		<TEGRA_SOCTHERM_THROT_LEVEL_MED>;
		};
		};
		};

Documentation/devicetree/bindings/thermal/qcom-tsens.txt

+14 −0

Original line number	Diff line number	Diff line
		@@ -6,11 +6,14 @@ Required properties:
		- "qcom,msm8916-tsens" (MSM8916)
		- "qcom,msm8974-tsens" (MSM8974)
		- "qcom,msm8996-tsens" (MSM8996)
		- "qcom,qcs404-tsens", "qcom,tsens-v1" (QCS404)
		- "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998)
		- "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845)
		The generic "qcom,tsens-v2" property must be used as a fallback for any SoC
		with version 2 of the TSENS IP. MSM8996 is the only exception because the
		generic property did not exist when support was added.
		Similarly, the generic "qcom,tsens-v1" property must be used as a fallback for
		any SoC with version 1 of the TSENS IP.

		- reg: Address range of the thermal registers.
		New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM
		@@ -39,3 +42,14 @@ tsens0: thermal-sensor@c263000 {
		#qcom,sensors = <13>;
		#thermal-sensor-cells = <1>;
		};

		Example 3 (for any platform containing v1 of the TSENS IP):
		tsens: thermal-sensor@4a9000 {
		compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
		reg = <0x004a9000 0x1000>, /* TM */
		<0x004a8000 0x1000>; /* SROT */
		nvmem-cells = <&tsens_caldata>;
		nvmem-cell-names = "calib";
		#qcom,sensors = <10>;
		#thermal-sensor-cells = <1>;
		};

Documentation/devicetree/bindings/thermal/rockchip-thermal.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -2,6 +2,7 @@

		Required properties:
		- compatible : should be "rockchip,<name>-tsadc"
		"rockchip,px30-tsadc": found on PX30 SoCs
		"rockchip,rv1108-tsadc": found on RV1108 SoCs
		"rockchip,rk3228-tsadc": found on RK3228 SoCs
		"rockchip,rk3288-tsadc": found on RK3288 SoCs

Documentation/devicetree/bindings/thermal/thermal-generic-adc.txt

+8 −2

Original line number	Diff line number	Diff line
		@@ -8,16 +8,22 @@ temperature using voltage-temperature lookup table.
		Required properties:
		===================
		- compatible: Must be "generic-adc-thermal".
		- #thermal-sensor-cells: Should be 1. See ./thermal.txt for a description
		of this property.
		Optional properties:
		===================
		- temperature-lookup-table: Two dimensional array of Integer; lookup table
		to map the relation between ADC value and
		temperature. When ADC is read, the value is
		looked up on the table to get the equivalent
		temperature.

		The first value of the each row of array is the
		temperature in milliCelsius and second value of
		the each row of array is the ADC read value.
		- #thermal-sensor-cells: Should be 1. See ./thermal.txt for a description
		of this property.

		If not specified, driver assumes the ADC channel
		gives milliCelsius directly.

		Example :
		#include <dt-bindings/thermal/thermal.h>

Admin message