Commit a4031afb authored Feb 09, 2020 by Christophe Leroy Committed by Michael Ellerman Feb 17, 2020

powerpc/8xx: Fix clearing of bits 20-23 in ITLB miss

In ITLB miss handled the line supposed to clear bits 20-23 on the L2
ITLB entry is buggy and does indeed nothing, leading to undefined
value which could allow execution when it shouldn't.

Properly do the clearing with the relevant instruction.

Fixes: 74fabcad ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers")
Cc: stable@vger.kernel.org # v5.0+
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Leonardo Bras <leonardo@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/4f70c2778163affce8508a210f65d140e84524b4.1581272050.git.christophe.leroy@c-s.fr

parent 50a175dd

arch/powerpc/kernel/head_8xx.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -256,7 +256,7 @@ InstructionTLBMiss:
		* set. All other Linux PTE bits control the behavior
		* of the MMU.
		*/
		rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
		rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
		rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
		ori r10, r10, RPN_PATTERN \| 0x200 /* Set 22 and 24-27 */
		mtspr SPRN_MI_RPN, r10 /* Update TLB entry */