Commit a4023f68 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Catalin Marinas
Browse files

arm64: Add hypervisor safe helper for checking constant capabilities 



The hypervisor may not have full access to the kernel data structures
and hence cannot safely use cpus_have_cap() helper for checking the
system capability. Add a safe helper for hypervisors to check a constant
system capability, which *doesn't* fall back to checking the bitmap
maintained by the kernel. With this, make the cpus_have_cap() only
check the bitmask and force constant cap checks to use the new API
for quicker checks.

Cc: Robert Ritcher <rritcher@cavium.com>
Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent c02433dd

arch/arm64/include/asm/cpufeature.h

+12 −7
Original line number Diff line number Diff line
@@ -9,8 +9,6 @@ 
#ifndef __ASM_CPUFEATURE_H

#define __ASM_CPUFEATURE_H



#include <linux/jump_label.h>



#include <asm/hwcap.h>

#include <asm/sysreg.h>
@@ -45,6 +43,8 @@ 


#ifndef __ASSEMBLY__



#include <linux/bug.h>

#include <linux/jump_label.h>

#include <linux/kernel.h>



/* CPU feature register tracking */
@@ -122,13 +122,18 @@ static inline bool cpu_have_feature(unsigned int num) 
	return elf_hwcap & (1UL << num);

}



static inline bool cpus_have_cap(unsigned int num)

/* System capability check for constant caps */

static inline bool cpus_have_const_cap(int num)

{

	if (num >= ARM64_NCAPS)

		return false;

	if (__builtin_constant_p(num))

	return static_branch_unlikely(&cpu_hwcap_keys[num]);

	else

}



static inline bool cpus_have_cap(unsigned int num)

{

	if (num >= ARM64_NCAPS)

		return false;

	return test_bit(num, cpu_hwcaps);

}
@@ -218,7 +223,7 @@ static inline bool cpu_supports_mixed_endian_el0(void) 


static inline bool system_supports_32bit_el0(void)

{

	return cpus_have_cap(ARM64_HAS_32BIT_EL0);

	return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);

}



static inline bool system_supports_mixed_endian_el0(void)

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -1102,5 +1102,5 @@ void __init setup_cpu_features(void) 
static bool __maybe_unused

cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)

{

	return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));

	return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));

}

arch/arm64/kernel/process.c

+1 −1
Original line number Diff line number Diff line
@@ -283,7 +283,7 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, 
		memset(childregs, 0, sizeof(struct pt_regs));

		childregs->pstate = PSR_MODE_EL1h;

		if (IS_ENABLED(CONFIG_ARM64_UAO) &&

		    cpus_have_cap(ARM64_HAS_UAO))

		    cpus_have_const_cap(ARM64_HAS_UAO))

			childregs->pstate |= PSR_UAO_BIT;

		p->thread.cpu_context.x19 = stack_start;

		p->thread.cpu_context.x20 = stk_sz;

drivers/irqchip/irq-gic-v3.c

+1 −12
Original line number Diff line number Diff line
@@ -120,11 +120,10 @@ static void gic_redist_wait_for_rwp(void) 
}



#ifdef CONFIG_ARM64

static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx);



static u64 __maybe_unused gic_read_iar(void)

{

	if (static_branch_unlikely(&is_cavium_thunderx))

	if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))

		return gic_read_iar_cavium_thunderx();

	else

		return gic_read_iar_common();
@@ -905,14 +904,6 @@ static const struct irq_domain_ops partition_domain_ops = { 
	.select = gic_irq_domain_select,

};



static void gicv3_enable_quirks(void)

{

#ifdef CONFIG_ARM64

	if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154))

		static_branch_enable(&is_cavium_thunderx);

#endif

}



static int __init gic_init_bases(void __iomem *dist_base,

				 struct redist_region *rdist_regs,

				 u32 nr_redist_regions,
@@ -935,8 +926,6 @@ static int __init gic_init_bases(void __iomem *dist_base, 
	gic_data.nr_redist_regions = nr_redist_regions;

	gic_data.redist_stride = redist_stride;



	gicv3_enable_quirks();



	/*

	 * Find out how many interrupts are supported.

	 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)

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