Commit a3ed353c authored by Shirish S's avatar Shirish S Committed by Alex Deucher
Browse files

amdgpu/gmc_v9: save/restore sdpif regs during S3 



fixes S3 issue with IOMMU + S/G  enabled @ 64M VRAM.

Suggested-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarShirish S <shirish.s@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 4829f898

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+1 −0
Original line number Diff line number Diff line
@@ -195,6 +195,7 @@ struct amdgpu_gmc { 
	uint32_t                srbm_soft_reset;

	bool			prt_warning;

	uint64_t		stolen_size;

	uint32_t		sdpif_register;

	/* apertures */

	u64			shared_aperture_start;

	u64			shared_aperture_end;

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+36 −1
Original line number Diff line number Diff line
@@ -1271,6 +1271,19 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 
	}

}



/**

 * gmc_v9_0_restore_registers - restores regs

 *

 * @adev: amdgpu_device pointer

 *

 * This restores register values, saved at suspend.

 */

static void gmc_v9_0_restore_registers(struct amdgpu_device *adev)

{

	if (adev->asic_type == CHIP_RAVEN)

		WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);

}



/**

 * gmc_v9_0_gart_enable - gart enable

 *
@@ -1376,6 +1389,20 @@ static int gmc_v9_0_hw_init(void *handle) 
	return r;

}



/**

 * gmc_v9_0_save_registers - saves regs

 *

 * @adev: amdgpu_device pointer

 *

 * This saves potential register values that should be

 * restored upon resume

 */

static void gmc_v9_0_save_registers(struct amdgpu_device *adev)

{

	if (adev->asic_type == CHIP_RAVEN)

		adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);

}



/**

 * gmc_v9_0_gart_disable - gart disable

 *
@@ -1412,9 +1439,16 @@ static int gmc_v9_0_hw_fini(void *handle) 


static int gmc_v9_0_suspend(void *handle)

{

	int r;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	return gmc_v9_0_hw_fini(adev);

	r = gmc_v9_0_hw_fini(adev);

	if (r)

		return r;



	gmc_v9_0_save_registers(adev);



	return 0;

}



static int gmc_v9_0_resume(void *handle)
@@ -1422,6 +1456,7 @@ static int gmc_v9_0_resume(void *handle) 
	int r;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	gmc_v9_0_restore_registers(adev);

	r = gmc_v9_0_hw_init(adev);

	if (r)

		return r;

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

+2 −0
Original line number Diff line number Diff line
@@ -7376,6 +7376,8 @@ 
#define mmCRTC4_CRTC_DRR_CONTROL                                                                       0x0f3e

#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX                                                              2













#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x395d













#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2





























// addressBlock: dce_dc_fmt4_dispdec















// base address: 0x2000



























































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