Commit a3dc838d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-4.16-soc-2' of... 

Merge tag 'tegra-for-4.16-soc-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc

Pull "soc/tegra: Changes for v4.16-rc1" from Thierry Reding:

Fuse and chip ID support for Tegra186 is added in this set of changes,
followed by some unification work for the PMC driver in order to avoid
code duplication between Tegra186 and prior chips.

This also contains a couple of fixes for reading fuses on Tegra20.

* tag 'tegra-for-4.16-soc-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: fuse: Explicitly request DMA channel from APB DMA driver
  soc/tegra: fuse: Fix reading registers using DMA on Tegra20
  soc/tegra: pmc: Consolidate Tegra186 support
  soc/tegra: pmc: Parameterize driver
  soc/tegra: fuse: Add Tegra186 chip ID support
  soc/tegra: fuse: Warn if accessing unmapped registers
  soc/tegra: fuse: Move register mapping check
  soc/tegra: fuse: Add Tegra186 support
  dt-bindings: misc: Add Tegra186 MISC registers bindings
parents 7294f2fc ccf15184

Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt

0 → 100644
+12 −0
Original line number Diff line number Diff line 
NVIDIA Tegra186 MISC register block



The MISC register block found on Tegra186 SoCs contains registers that can be

used to identify a given chip and various strapping options.



Required properties:

- compatible: Must be:

  - Tegra186: "nvidia,tegra186-misc"

- reg: Should contain 2 entries: The first entry gives the physical address

       and length of the register region which contains revision and debug

       features. The second entry specifies the physical address and length

       of the register region indicating the strapping options.

drivers/soc/tegra/Kconfig

+1 −4
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ config ARCH_TEGRA_186_SOC 
	select TEGRA_BPMP

	select TEGRA_HSP_MBOX

	select TEGRA_IVC

	select SOC_TEGRA_PMC_TEGRA186

	select SOC_TEGRA_PMC

	help

	  Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a

	  combination of Denver and Cortex-A57 CPU cores and a GPU based on
@@ -118,9 +118,6 @@ config SOC_TEGRA_FLOWCTRL 
config SOC_TEGRA_PMC

	bool



config SOC_TEGRA_PMC_TEGRA186

	bool



config SOC_TEGRA_POWERGATE_BPMP

	def_bool y

	depends on PM_GENERIC_DOMAINS

drivers/soc/tegra/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -4,5 +4,4 @@ obj-y += fuse/ 
obj-y += common.o

obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o

obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o

obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o

obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o

drivers/soc/tegra/fuse/fuse-tegra.c

+4 −0
Original line number Diff line number Diff line
@@ -103,6 +103,9 @@ static struct tegra_fuse *fuse = &(struct tegra_fuse) { 
};



static const struct of_device_id tegra_fuse_match[] = {

#ifdef CONFIG_ARCH_TEGRA_186_SOC

	{ .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },

#endif

#ifdef CONFIG_ARCH_TEGRA_210_SOC

	{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },

#endif
@@ -132,6 +135,7 @@ static int tegra_fuse_probe(struct platform_device *pdev) 


	/* take over the memory region from the early initialization */

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	fuse->phys = res->start;

	fuse->base = devm_ioremap_resource(&pdev->dev, res);

	if (IS_ERR(fuse->base))

		return PTR_ERR(fuse->base);

drivers/soc/tegra/fuse/fuse-tegra20.c

+11 −2
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset) 


	mutex_lock(&fuse->apbdma.lock);



	fuse->apbdma.config.src_addr = fuse->apbdma.phys + FUSE_BEGIN + offset;

	fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset;



	err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config);

	if (err)
@@ -96,6 +96,13 @@ out: 
	return value;

}



static bool dma_filter(struct dma_chan *chan, void *filter_param)

{

	struct device_node *np = chan->device->dev->of_node;



	return of_device_is_compatible(np, "nvidia,tegra20-apbdma");

}



static int tegra20_fuse_probe(struct tegra_fuse *fuse)

{

	dma_cap_mask_t mask;
@@ -103,7 +110,7 @@ static int tegra20_fuse_probe(struct tegra_fuse *fuse) 
	dma_cap_zero(mask);

	dma_cap_set(DMA_SLAVE, mask);



	fuse->apbdma.chan = dma_request_channel(mask, NULL, NULL);

	fuse->apbdma.chan = __dma_request_channel(&mask, dma_filter, NULL);

	if (!fuse->apbdma.chan)

		return -EPROBE_DEFER;
@@ -119,6 +126,8 @@ static int tegra20_fuse_probe(struct tegra_fuse *fuse) 
	fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;

	fuse->apbdma.config.src_maxburst = 1;

	fuse->apbdma.config.dst_maxburst = 1;

	fuse->apbdma.config.direction = DMA_DEV_TO_MEM;

	fuse->apbdma.config.device_fc = false;



	init_completion(&fuse->apbdma.wait);

	mutex_init(&fuse->apbdma.lock);

CRA Git | Maintained and supported by SUSTech CRA and CCSE