Commit a3cff3e6 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-drivers-for-v5.9-tag1' of... 

Merge tag 'renesas-drivers-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.9

  - Add core support for the new RZ/G2H (R8A774E1) SoC, including System
    Controller (SYSC) and Reset (RST) support.

* tag 'renesas-drivers-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-rst: Add support for RZ/G2H
  soc: renesas: Identify RZ/G2H
  soc: renesas: Add Renesas R8A774E1 config option
  soc: renesas: rcar-sysc: Add r8a774e1 support
  clk: renesas: Add r8a774e1 CPG Core Clock Definitions
  dt-bindings: power: Add r8a774e1 SYSC power domain definitions

Link: https://lore.kernel.org/r/20200717112427.26032-3-geert+renesas@glider.be


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7247e1f1 7f8fa833

drivers/soc/renesas/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -201,6 +201,13 @@ config ARCH_R8A774C0 
	help

	  This enables support for the Renesas RZ/G2E SoC.



config ARCH_R8A774E1

	bool "Renesas RZ/G2H SoC Platform"

	select ARCH_RCAR_GEN3

	select SYSC_R8A774E1

	help

	  This enables support for the Renesas RZ/G2H SoC.



config ARCH_R8A77950

	bool "Renesas R-Car H3 ES1.x SoC Platform"

	select ARCH_RCAR_GEN3
@@ -296,6 +303,10 @@ config SYSC_R8A774C0 
	bool "RZ/G2E System Controller support" if COMPILE_TEST

	select SYSC_RCAR



config SYSC_R8A774E1

	bool "RZ/G2H System Controller support" if COMPILE_TEST

	select SYSC_RCAR



config SYSC_R8A7779

	bool "R-Car H1 System Controller support" if COMPILE_TEST

	select SYSC_RCAR

drivers/soc/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o 
obj-$(CONFIG_SYSC_R8A774A1)	+= r8a774a1-sysc.o

obj-$(CONFIG_SYSC_R8A774B1)	+= r8a774b1-sysc.o

obj-$(CONFIG_SYSC_R8A774C0)	+= r8a774c0-sysc.o

obj-$(CONFIG_SYSC_R8A774E1)	+= r8a774e1-sysc.o

obj-$(CONFIG_SYSC_R8A7779)	+= r8a7779-sysc.o

obj-$(CONFIG_SYSC_R8A7790)	+= r8a7790-sysc.o

obj-$(CONFIG_SYSC_R8A7791)	+= r8a7791-sysc.o

drivers/soc/renesas/r8a774e1-sysc.c

0 → 100644
+43 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Renesas RZ/G2H System Controller

 * Copyright (C) 2020 Renesas Electronics Corp.

 *

 * Based on Renesas R-Car H3 System Controller

 * Copyright (C) 2016-2017 Glider bvba

 */



#include <linux/kernel.h>



#include <dt-bindings/power/r8a774e1-sysc.h>



#include "rcar-sysc.h"



static const struct rcar_sysc_area r8a774e1_areas[] __initconst = {

	{ "always-on",	    0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },

	{ "ca57-scu",	0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },

	{ "ca57-cpu0",	 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },

	{ "ca57-cpu1",	 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },

	{ "ca57-cpu2",	 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },

	{ "ca57-cpu3",	 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },

	{ "ca53-scu",	0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },

	{ "ca53-cpu0",	0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },

	{ "ca53-cpu1",	0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },

	{ "ca53-cpu2",	0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },

	{ "ca53-cpu3",	0x200, 3, R8A774E1_PD_CA53_CPU3, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },

	{ "a3vp",	0x340, 0, R8A774E1_PD_A3VP, R8A774E1_PD_ALWAYS_ON },

	{ "a3vc",	0x380, 0, R8A774E1_PD_A3VC, R8A774E1_PD_ALWAYS_ON },

	{ "a2vc1",	0x3c0, 1, R8A774E1_PD_A2VC1, R8A774E1_PD_A3VC },

	{ "3dg-a",	0x100, 0, R8A774E1_PD_3DG_A, R8A774E1_PD_ALWAYS_ON },

	{ "3dg-b",	0x100, 1, R8A774E1_PD_3DG_B, R8A774E1_PD_3DG_A },

	{ "3dg-c",	0x100, 2, R8A774E1_PD_3DG_C, R8A774E1_PD_3DG_B },

	{ "3dg-d",	0x100, 3, R8A774E1_PD_3DG_D, R8A774E1_PD_3DG_C },

	{ "3dg-e",	0x100, 4, R8A774E1_PD_3DG_E, R8A774E1_PD_3DG_D },

};



const struct rcar_sysc_info r8a774e1_sysc_info __initconst = {

	.areas = r8a774e1_areas,

	.num_areas = ARRAY_SIZE(r8a774e1_areas),

	.extmask_offs = 0x2f8,

	.extmask_val = BIT(0),

};

drivers/soc/renesas/rcar-rst.c

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { 
	{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },

	{ .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },

	{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },

	{ .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },

	/* R-Car Gen1 */

	{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },

	{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },

drivers/soc/renesas/rcar-sysc.c

+3 −0
Original line number Diff line number Diff line
@@ -296,6 +296,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = { 
#ifdef CONFIG_SYSC_R8A774C0

	{ .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },

#endif

#ifdef CONFIG_SYSC_R8A774E1

	{ .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },

#endif

#ifdef CONFIG_SYSC_R8A7779

	{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },

#endif

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