Commit a3ae5499 authored by Owen Chen's avatar Owen Chen Committed by Stephen Boyd
Browse files

clk: mediatek: Add new clkmux register API 



On both MT8183 & MT6765, there add "set/clr" register for
each clkmux setting, and one update register to trigger value change.
It is designed to prevent read-modify-write racing issue.
The sw design need to add a new API to handle this hw change with
a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".

Signed-off-by: default avatarOwen Chen <owen.chen@mediatek.com>
Signed-off-by: default avatarWeiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: default avatarNicolas Boichat <drinkcat@chromium.org>
Tested-by: default avatarNicolas Boichat <drinkcat@chromium.org>
[sboyd@kernel.org: Squash in flags=0 to silence warning]
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent be17ca6a

drivers/clk/mediatek/Makefile

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# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o

obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o



obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o

obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o

obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o

drivers/clk/mediatek/clk-mux.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2018 MediaTek Inc.

 * Author: Owen Chen <owen.chen@mediatek.com>

 */



#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/slab.h>

#include <linux/mfd/syscon.h>



#include "clk-mtk.h"

#include "clk-mux.h"



static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)

{

	return container_of(hw, struct mtk_clk_mux, hw);

}



static int mtk_clk_mux_enable(struct clk_hw *hw)

{

	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);

	u32 mask = BIT(mux->data->gate_shift);



	return regmap_update_bits(mux->regmap, mux->data->mux_ofs,

			mask, ~mask);

}



static void mtk_clk_mux_disable(struct clk_hw *hw)

{

	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);

	u32 mask = BIT(mux->data->gate_shift);



	regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);

}



static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)

{

	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);



	return regmap_write(mux->regmap, mux->data->clr_ofs,

			BIT(mux->data->gate_shift));

}



static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)

{

	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);



	regmap_write(mux->regmap, mux->data->set_ofs,

			BIT(mux->data->gate_shift));

}



static int mtk_clk_mux_is_enabled(struct clk_hw *hw)

{

	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);

	u32 val;



	regmap_read(mux->regmap, mux->data->mux_ofs, &val);



	return (val & BIT(mux->data->gate_shift)) == 0;

}



static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)

{

	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);

	u32 mask = GENMASK(mux->data->mux_width - 1, 0);

	u32 val;



	regmap_read(mux->regmap, mux->data->mux_ofs, &val);

	val = (val >> mux->data->mux_shift) & mask;



	return val;

}



static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)

{

	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);

	u32 mask = GENMASK(mux->data->mux_width - 1, 0);

	unsigned long flags = 0;



	if (mux->lock)

		spin_lock_irqsave(mux->lock, flags);

	else

		__acquire(mux->lock);



	regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,

		index << mux->data->mux_shift);



	if (mux->lock)

		spin_unlock_irqrestore(mux->lock, flags);

	else

		__release(mux->lock);



	return 0;

}



static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)

{

	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);

	u32 mask = GENMASK(mux->data->mux_width - 1, 0);

	u32 val, orig;

	unsigned long flags = 0;



	if (mux->lock)

		spin_lock_irqsave(mux->lock, flags);

	else

		__acquire(mux->lock);



	regmap_read(mux->regmap, mux->data->mux_ofs, &orig);

	val = (orig & ~(mask << mux->data->mux_shift))

			| (index << mux->data->mux_shift);



	if (val != orig) {

		regmap_write(mux->regmap, mux->data->clr_ofs,

				mask << mux->data->mux_shift);

		regmap_write(mux->regmap, mux->data->set_ofs,

				index << mux->data->mux_shift);



		if (mux->data->upd_shift >= 0)

			regmap_write(mux->regmap, mux->data->upd_ofs,

					BIT(mux->data->upd_shift));

	}



	if (mux->lock)

		spin_unlock_irqrestore(mux->lock, flags);

	else

		__release(mux->lock);



	return 0;

}



const struct clk_ops mtk_mux_ops = {

	.get_parent = mtk_clk_mux_get_parent,

	.set_parent = mtk_clk_mux_set_parent_lock,

};



const struct clk_ops mtk_mux_clr_set_upd_ops = {

	.get_parent = mtk_clk_mux_get_parent,

	.set_parent = mtk_clk_mux_set_parent_setclr_lock,

};



const struct clk_ops mtk_mux_gate_ops = {

	.enable = mtk_clk_mux_enable,

	.disable = mtk_clk_mux_disable,

	.is_enabled = mtk_clk_mux_is_enabled,

	.get_parent = mtk_clk_mux_get_parent,

	.set_parent = mtk_clk_mux_set_parent_lock,

};



const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {

	.enable = mtk_clk_mux_enable_setclr,

	.disable = mtk_clk_mux_disable_setclr,

	.is_enabled = mtk_clk_mux_is_enabled,

	.get_parent = mtk_clk_mux_get_parent,

	.set_parent = mtk_clk_mux_set_parent_setclr_lock,

};



struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,

				 struct regmap *regmap,

				 spinlock_t *lock)

{

	struct mtk_clk_mux *clk_mux;

	struct clk_init_data init;

	struct clk *clk;



	clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);

	if (!clk_mux)

		return ERR_PTR(-ENOMEM);



	init.name = mux->name;

	init.flags = mux->flags | CLK_SET_RATE_PARENT;

	init.parent_names = mux->parent_names;

	init.num_parents = mux->num_parents;

	init.ops = mux->ops;



	clk_mux->regmap = regmap;

	clk_mux->data = mux;

	clk_mux->lock = lock;

	clk_mux->hw.init = &init;



	clk = clk_register(NULL, &clk_mux->hw);

	if (IS_ERR(clk)) {

		kfree(clk_mux);

		return clk;

	}



	return clk;

}



int mtk_clk_register_muxes(const struct mtk_mux *muxes,

			   int num, struct device_node *node,

			   spinlock_t *lock,

			   struct clk_onecell_data *clk_data)

{

	struct regmap *regmap;

	struct clk *clk;

	int i;



	regmap = syscon_node_to_regmap(node);

	if (IS_ERR(regmap)) {

		pr_err("Cannot find regmap for %pOF: %ld\n", node,

		       PTR_ERR(regmap));

		return PTR_ERR(regmap);

	}



	for (i = 0; i < num; i++) {

		const struct mtk_mux *mux = &muxes[i];



		if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {

			clk = mtk_clk_register_mux(mux, regmap, lock);



			if (IS_ERR(clk)) {

				pr_err("Failed to register clk %s: %ld\n",

				       mux->name, PTR_ERR(clk));

				continue;

			}



			clk_data->clks[mux->id] = clk;

		}

	}



	return 0;

}

drivers/clk/mediatek/clk-mux.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2018 MediaTek Inc.

 * Author: Owen Chen <owen.chen@mediatek.com>

 */



#ifndef __DRV_CLK_MTK_MUX_H

#define __DRV_CLK_MTK_MUX_H



#include <linux/clk-provider.h>



struct mtk_clk_mux {

	struct clk_hw hw;

	struct regmap *regmap;

	const struct mtk_mux *data;

	spinlock_t *lock;

};



struct mtk_mux {

	int id;

	const char *name;

	const char * const *parent_names;

	unsigned int flags;



	u32 mux_ofs;

	u32 set_ofs;

	u32 clr_ofs;

	u32 upd_ofs;



	u8 mux_shift;

	u8 mux_width;

	u8 gate_shift;

	s8 upd_shift;



	const struct clk_ops *ops;



	signed char num_parents;

};



extern const struct clk_ops mtk_mux_ops;

extern const struct clk_ops mtk_mux_clr_set_upd_ops;

extern const struct clk_ops mtk_mux_gate_ops;

extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;



#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,		\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			_gate, _upd_ofs, _upd, _flags, _ops) {		\

		.id = _id,						\

		.name = _name,						\

		.mux_ofs = _mux_ofs,					\

		.set_ofs = _mux_set_ofs,				\

		.clr_ofs = _mux_clr_ofs,				\

		.upd_ofs = _upd_ofs,					\

		.mux_shift = _shift,					\

		.mux_width = _width,					\

		.gate_shift = _gate,					\

		.upd_shift = _upd,					\

		.parent_names = _parents,				\

		.num_parents = ARRAY_SIZE(_parents),			\

		.flags = _flags,					\

		.ops = &_ops,						\

	}



#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,	\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			_gate, _upd_ofs, _upd, _flags)			\

		GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,	\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			_gate, _upd_ofs, _upd, _flags,			\

			mtk_mux_gate_clr_set_upd_ops)



#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,		\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			_gate, _upd_ofs, _upd)				\

		MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents,	\

			_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift,	\

			_width, _gate, _upd_ofs, _upd,			\

			CLK_SET_RATE_PARENT)



struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,

				 struct regmap *regmap,

				 spinlock_t *lock);



int mtk_clk_register_muxes(const struct mtk_mux *muxes,

			   int num, struct device_node *node,

			   spinlock_t *lock,

			   struct clk_onecell_data *clk_data);



#endif /* __DRV_CLK_MTK_MUX_H */

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