Merge tag 'asoc-v3.20-2' of...

Bindings for I2S controller built into xtfpga Xtensa bitstreams.

Required properties:

- compatible: shall be "cdns,xtfpga-i2s".

- reg: memory region (address and length) with device registers.

- interrupts: interrupt for the device.

- clocks: phandle to the clk used as master clock. I2S bus clock

  is derived from it.

Examples:

	i2s0: xtfpga-i2s@0d080000 {

		#sound-dai-cells = <0>;

		compatible = "cdns,xtfpga-i2s";

		reg = <0x0d080000 0x40>;

		interrupts = <2 1>;

		clocks = <&cdce706 4>;

	};

DesignWare I2S controller

Required properties:

 - compatible : Must be "snps,designware-i2s"

 - reg : Must contain the I2S core's registers location and length

 - clocks : Pairs of phandle and specifier referencing the controller's

   clocks. The controller expects one clock: the clock used as the sampling

   rate reference clock sample.

 - clock-names : "i2sclk" for the sample rate reference clock.

 - dmas: Pairs of phandle and specifier for the DMA channels that are used by

   the core. The core expects one or two dma channels: one for transmit and

   one for receive.

 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.

For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'

properties please check:

	* resource-names.txt

	* clock/clock-bindings.txt

	* dma/dma.txt

Example:

	soc_i2s: i2s@7ff90000 {

		compatible = "snps,designware-i2s";

		reg = <0x0 0x7ff90000 0x0 0x1000>;

		clocks = <&scpi_i2sclk 0>;

		clock-names = "i2sclk";

		#sound-dai-cells = <0>;

		dmas = <&dma0 5>;

		dma-names = "tx";

	};

NVIDIA Tegra audio complex, with RT5677 CODEC

Required properties:

- compatible : "nvidia,tegra-audio-rt5677"

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names : Must include the following entries:

  - pll_a

  - pll_a_out0

  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)

- nvidia,model : The user-visible name of this sound complex.

- nvidia,audio-routing : A list of the connections between audio components.

  Each entry is a pair of strings, the first being the connection's sink,

  the second being the connection's source. Valid names for sources and

  sinks are the RT5677's pins (as documented in its binding), and the jacks

  on the board:

  * Headphone

  * Speaker

  * Headset Mic

  * Internal Mic 1

  * Internal Mic 2

- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's

  connected to the CODEC.

- nvidia,audio-codec : The phandle of the RT5677 audio codec. This binding

  assumes that AIF1 on the CODEC is connected to Tegra.

Optional properties:

- nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in

- nvidia,hp-en-gpios : The GPIO that enables headphone amplifier

- nvidia,mic-present-gpios: The GPIO that mic jack is plugged in

- nvidia,dmic-clk-en-gpios : The GPIO that gates DMIC clock signal

Example:

sound {

	compatible = "nvidia,tegra-audio-rt5677-ryu",

	        "nvidia,tegra-audio-rt5677";

	nvidia,model = "NVIDIA Tegra Ryu";

	nvidia,audio-routing =

		"Headphone", "LOUT2",

		"Headphone", "LOUT1",

		"Headset Mic", "MICBIAS1",

		"IN1P", "Headset Mic",

		"IN1N", "Headset Mic",

		"DMIC L1", "Internal Mic 1",

		"DMIC R1", "Internal Mic 1",

		"DMIC L2", "Internal Mic 2",

		"DMIC R2", "Internal Mic 2",

		"Speaker", "PDM1L",

		"Speaker", "PDM1R";

	nvidia,i2s-controller = <&tegra_i2s1>;

	nvidia,audio-codec = <&rt5677>;

	nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;

	nvidia,mic-present-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;

	nvidia,hp-en-gpios = <&rt5677 1 GPIO_ACTIVE_HIGH>;

	nvidia,dmic-clk-en-gpios = <&rt5677 2 GPIO_ACTIVE_HIGH>;

	clocks = <&tegra_car TEGRA124_CLK_PLL_A>,

	         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,

	         <&tegra_car TEGRA124_CLK_EXTERN1>;

	clock-names = "pll_a", "pll_a_out0", "mclk";

};

Optional properties:

  - clocks : A clock specifier for the clock connected as SCLK.  If this

    is absent the device will be configured to clock from BCLK.

    is absent the device will be configured to clock from BCLK.  If pll-in

    and pll-out are specified in addition to a clock, the device is

    configured to accept clock input on a specified gpio pin.

Example:

  - pll-in, pll-out : gpio pins used to connect the pll using <1>

    through <6>.  The device will be configured for clock input on the

    given pll-in pin and PLL output on the given pll-out pin.  An

    external connection from the pll-out pin to the SCLK pin is assumed.

Examples:

	pcm5122: pcm5122@4c {

		compatible = "ti,pcm5122";

		DVDD-supply = <&reg_1v8>;

		CPVDD-supply = <&reg_3v3>;

	};

	pcm5142: pcm5142@4c {

		compatible = "ti,pcm5142";

		reg = <0x4c>;

		AVDD-supply = <&reg_3v3_analog>;

		DVDD-supply = <&reg_1v8>;

		CPVDD-supply = <&reg_3v3>;

		clocks = <&sck>;

		pll-in = <3>;

		pll-out = <6>;

	};

  "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root

  clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2

  doesn't have any such mux.

- #clock-cells: should be 1, this property must be present if the I2S device

  is a clock provider in terms of the common clock bindings, described in

  ../clock/clock-bindings.txt.

- clock-output-names: from the common clock bindings, names of the CDCLK

  I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1",

  "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices recpectively.

There are following clocks available at the I2S device nodes:

 CLK_I2S_CDCLK    - the CDCLK (CODECLKO) gate clock,

 CLK_I2S_RCLK_PSR - the RCLK prescaler divider clock (corresponding to the

		    IISPSR register),

 CLK_I2S_RCLK_SRC - the RCLKSRC mux clock (corresponding to RCLKSRC bit in

		    IISMOD register).

Refer to the SoC datasheet for availability of the above clocks.

The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available

in the IIS Multi Audio Interface (I2S0).

Note: Old DTs may not have the #clock-cells, clock-output-names properties

and then not use the I2S node as a clock supplier.

Optional SoC Specific Properties:

- pinctrl-0: Should specify pin control groups used for this controller.

- pinctrl-names: Should contain only one value - "default".

Example:

i2s0: i2s@03830000 {

		<&clock_audss EXYNOS_I2S_BUS>,

		<&clock_audss EXYNOS_SCLK_I2S>;

	clock-names = "iis", "i2s_opclk0", "i2s_opclk1";

	#clock-cells;

	clock-output-names = "i2s_cdclk0";

	samsung,idma-addr = <0x03000000>;

	pinctrl-names = "default";

	pinctrl-0 = <&i2s0_bus>;