Commit a394cf6e authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch 'kvm-arm64/misc-5.9' into kvmarm-master/next-WIP 



Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents c9dc9500 a59a2edb

arch/arm64/Kconfig

+0 −16
Original line number Diff line number Diff line
@@ -1182,22 +1182,6 @@ config HARDEN_BRANCH_PREDICTOR 


	  If unsure, say Y.



config HARDEN_EL2_VECTORS

	bool "Harden EL2 vector mapping against system register leak" if EXPERT

	default y

	help

	  Speculation attacks against some high-performance processors can

	  be used to leak privileged information such as the vector base

	  register, resulting in a potential defeat of the EL2 layout

	  randomization.



	  This config option will map the vectors to a fixed location,

	  independent of the EL2 code mapping, so that revealing VBAR_EL2

	  to an attacker does not give away any extra information. This

	  only gets enabled on affected CPUs.



	  If unsure, say Y.



config ARM64_SSBD

	bool "Speculative Store Bypass Disable" if EXPERT

	default y

arch/arm64/include/asm/kvm_asm.h

+0 −1
Original line number Diff line number Diff line
@@ -191,7 +191,6 @@ extern char __smccc_workaround_1_smc[__SMCCC_WORKAROUND_1_SMC_SZ]; 
.macro get_vcpu_ptr vcpu, ctxt

	get_host_ctxt \ctxt, \vcpu

	ldr	\vcpu, [\ctxt, #HOST_CONTEXT_VCPU]

	kern_hyp_va	\vcpu

.endm



#endif

arch/arm64/include/asm/kvm_emulate.h

+17 −17
Original line number Diff line number Diff line
@@ -238,14 +238,14 @@ static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 
	return mode != PSR_MODE_EL0t;

}



static __always_inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)

static __always_inline u32 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu)

{

	return vcpu->arch.fault.esr_el2;

}



static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)

{

	u32 esr = kvm_vcpu_get_hsr(vcpu);

	u32 esr = kvm_vcpu_get_esr(vcpu);



	if (esr & ESR_ELx_CV)

		return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
@@ -270,64 +270,64 @@ static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 


static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;

	return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK;

}



static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV);

}



static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);

	return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);

}



static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE);

}



static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF);

}



static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)

{

	return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;

	return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;

}



static __always_inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW);

}



static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR) ||

		kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */

}



static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM);

}



static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)

{

	return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);

	return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);

}



/* This one is not specific to Data Abort */

static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL);

}



static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)

{

	return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));

	return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu));

}



static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
@@ -337,12 +337,12 @@ static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 


static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;

	return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC;

}



static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;

	return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE;

}



static __always_inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
@@ -366,7 +366,7 @@ static __always_inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu) 


static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)

{

	u32 esr = kvm_vcpu_get_hsr(vcpu);

	u32 esr = kvm_vcpu_get_esr(vcpu);

	return ESR_ELx_SYS64_ISS_RT(esr);

}

arch/arm64/kernel/cpu_errata.c

+2 −2
Original line number Diff line number Diff line
@@ -637,7 +637,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 
	return is_midr_in_range(midr, &range) && has_dic;

}



#if defined(CONFIG_HARDEN_EL2_VECTORS)

#ifdef CONFIG_RANDOMIZE_BASE



static const struct midr_range ca57_a72[] = {

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
@@ -882,7 +882,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = check_branch_predictor,

	},

#ifdef CONFIG_HARDEN_EL2_VECTORS

#ifdef CONFIG_RANDOMIZE_BASE

	{

		.desc = "EL2 vector hardening",

		.capability = ARM64_HARDEN_EL2_VECTORS,

arch/arm64/kvm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ config KVM_ARM_PMU 
	  virtual machines.



config KVM_INDIRECT_VECTORS

	def_bool HARDEN_BRANCH_PREDICTOR || HARDEN_EL2_VECTORS

	def_bool HARDEN_BRANCH_PREDICTOR || RANDOMIZE_BASE



endif # KVM

CRA Git | Maintained and supported by SUSTech CRA and CCSE