Commit a3947209 authored by Lars-Peter Clausen's avatar Lars-Peter Clausen Committed by Stephen Boyd
Browse files

clk: axi-clkgen: Set power bits for fractional mode 



Using the fractional dividers requires some additional power bits to be
set.

The fractional power bits are not documented and the current heuristic
for setting them seems be insufficient for some cases. Just always set all
the fractional power bits when in fractional mode.

Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: default avatarAlexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201001085948.21412-2-alexandru.ardelean@analog.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 86378cf6

drivers/clk/clk-axi-clkgen.c

+7 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#define MMCM_REG_LOCK1		0x18

#define MMCM_REG_LOCK2		0x19

#define MMCM_REG_LOCK3		0x1a

#define MMCM_REG_POWER		0x28

#define MMCM_REG_FILTER1	0x4e

#define MMCM_REG_FILTER2	0x4f
@@ -320,6 +321,7 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, 
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);

	unsigned int d, m, dout;

	struct axi_clkgen_div_params params;

	uint32_t power = 0;

	uint32_t filter;

	uint32_t lock;
@@ -331,6 +333,11 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, 
	if (d == 0 || dout == 0 || m == 0)

		return -EINVAL;



	if ((dout & 0x7) != 0 || (m & 0x7) != 0)

		power |= 0x9800;



	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);



	filter = axi_clkgen_lookup_filter(m - 1);

	lock = axi_clkgen_lookup_lock(m - 1);

CRA Git | Maintained and supported by SUSTech CRA and CCSE