Commit a3748463 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-v4.12-rc4' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "This is the main set of fixes for rc4, one amdgpu fix, some exynos
  regression fixes, some msm fixes and some i915 and GVT fixes.

  I've got a second regression fix for some DP chips that might be a
  bit large, but I think we'd like to land it now, I'll send it along
  tomorrow, once you are happy with this set"

* tag 'drm-fixes-for-v4.12-rc4' of git://people.freedesktop.org/~airlied/linux: (24 commits)
  drm/amdgpu: Program ring for vce instance 1 at its register space
  drm/exynos: clean up description of exynos_drm_crtc
  drm/exynos: dsi: Remove bridge node reference in removal
  drm/exynos: dsi: Fix the parse_dt function
  drm/exynos: Merge pre/postclose hooks
  drm/msm: Fix the check for the command size
  drm/msm: Take the mutex before calling msm_gem_new_impl
  drm/msm: for array in-fences, check if all backing fences are from our own context before waiting
  drm/msm: constify irq_domain_ops
  drm/msm/mdp5: release hwpipe(s) for unused planes
  drm/msm: Reuse dma_fence_release.
  drm/msm: Expose our reservation object when exporting a dmabuf.
  drm/msm/gpu: check legacy clk names in get_clocks()
  drm/msm/mdp5: use __drm_atomic_helper_plane_duplicate_state()
  drm/msm: select PM_OPP
  drm/i915: Stop pretending to mask/unmask LPE audio interrupts
  drm/i915/selftests: Silence compiler warning in igt_ctx_exec
  Revert "drm/i915: Restore lost "Initialized i915" welcome message"
  drm/i915/gvt: clean up unsubmited workloads before destroying kmem cache
  drm/i915/gvt: Disable compression workaround for Gen9
  ...
parents d602fb68 400129f0

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

+68 −27
Original line number Diff line number Diff line
@@ -77,13 +77,26 @@ static int vce_v3_0_set_clockgating_state(void *handle, 
static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	u32 v;



	mutex_lock(&adev->grbm_idx_mutex);

	if (adev->vce.harvest_config == 0 ||

		adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)

		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));

	else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)

		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));



	if (ring == &adev->vce.ring[0])

		return RREG32(mmVCE_RB_RPTR);

		v = RREG32(mmVCE_RB_RPTR);

	else if (ring == &adev->vce.ring[1])

		return RREG32(mmVCE_RB_RPTR2);

		v = RREG32(mmVCE_RB_RPTR2);

	else

		return RREG32(mmVCE_RB_RPTR3);

		v = RREG32(mmVCE_RB_RPTR3);



	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

	mutex_unlock(&adev->grbm_idx_mutex);



	return v;

}



/**
@@ -96,13 +109,26 @@ static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 
static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	u32 v;



	mutex_lock(&adev->grbm_idx_mutex);

	if (adev->vce.harvest_config == 0 ||

		adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)

		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));

	else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)

		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));



	if (ring == &adev->vce.ring[0])

		return RREG32(mmVCE_RB_WPTR);

		v = RREG32(mmVCE_RB_WPTR);

	else if (ring == &adev->vce.ring[1])

		return RREG32(mmVCE_RB_WPTR2);

		v = RREG32(mmVCE_RB_WPTR2);

	else

		return RREG32(mmVCE_RB_WPTR3);

		v = RREG32(mmVCE_RB_WPTR3);



	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

	mutex_unlock(&adev->grbm_idx_mutex);



	return v;

}



/**
@@ -116,12 +142,22 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 
{

	struct amdgpu_device *adev = ring->adev;



	mutex_lock(&adev->grbm_idx_mutex);

	if (adev->vce.harvest_config == 0 ||

		adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)

		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));

	else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)

		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));



	if (ring == &adev->vce.ring[0])

		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

	else if (ring == &adev->vce.ring[1])

		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

	else

		WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));



	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

	mutex_unlock(&adev->grbm_idx_mutex);

}



static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
@@ -231,6 +267,16 @@ static int vce_v3_0_start(struct amdgpu_device *adev) 
	struct amdgpu_ring *ring;

	int idx, r;



	mutex_lock(&adev->grbm_idx_mutex);

	for (idx = 0; idx < 2; ++idx) {

		if (adev->vce.harvest_config & (1 << idx))

			continue;



		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));



		/* Program instance 0 reg space for two instances or instance 0 case

		program instance 1 reg space for only instance 1 available case */

		if (idx != 1 || adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) {

			ring = &adev->vce.ring[0];

			WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));

			WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
@@ -251,13 +297,8 @@ static int vce_v3_0_start(struct amdgpu_device *adev) 
			WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);

			WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));

			WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);

		}



	mutex_lock(&adev->grbm_idx_mutex);

	for (idx = 0; idx < 2; ++idx) {

		if (adev->vce.harvest_config & (1 << idx))

			continue;



		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));

		vce_v3_0_mc_resume(adev, idx);

		WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);

drivers/gpu/drm/exynos/exynos_drm_drv.c

+1 −7
Original line number Diff line number Diff line
@@ -82,14 +82,9 @@ err_file_priv_free: 
	return ret;

}



static void exynos_drm_preclose(struct drm_device *dev,

					struct drm_file *file)

{

	exynos_drm_subdrv_close(dev, file);

}



static void exynos_drm_postclose(struct drm_device *dev, struct drm_file *file)

{

	exynos_drm_subdrv_close(dev, file);

	kfree(file->driver_priv);

	file->driver_priv = NULL;

}
@@ -145,7 +140,6 @@ static struct drm_driver exynos_drm_driver = { 
	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME

				  | DRIVER_ATOMIC | DRIVER_RENDER,

	.open			= exynos_drm_open,

	.preclose		= exynos_drm_preclose,

	.lastclose		= exynos_drm_lastclose,

	.postclose		= exynos_drm_postclose,

	.gem_free_object_unlocked = exynos_drm_gem_free_object,

drivers/gpu/drm/exynos/exynos_drm_drv.h

+1 −4
Original line number Diff line number Diff line
@@ -160,12 +160,9 @@ struct exynos_drm_clk { 
 *	drm framework doesn't support multiple irq yet.

 *	we can refer to the crtc to current hardware interrupt occurred through

 *	this pipe value.

 * @enabled: if the crtc is enabled or not

 * @event: vblank event that is currently queued for flip

 * @wait_update: wait all pending planes updates to finish

 * @pending_update: number of pending plane updates in this crtc

 * @ops: pointer to callbacks for exynos drm specific functionality

 * @ctx: A pointer to the crtc's implementation specific context

 * @pipe_clk: A pointer to the crtc's pipeline clock.

 */

struct exynos_drm_crtc {

	struct drm_crtc			base;

drivers/gpu/drm/exynos/exynos_drm_dsi.c

+9 −17
Original line number Diff line number Diff line
@@ -1633,7 +1633,6 @@ static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 
{

	struct device *dev = dsi->dev;

	struct device_node *node = dev->of_node;

	struct device_node *ep;

	int ret;



	ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
@@ -1641,32 +1640,21 @@ static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 
	if (ret < 0)

		return ret;



	ep = of_graph_get_endpoint_by_regs(node, DSI_PORT_OUT, 0);

	if (!ep) {

		dev_err(dev, "no output port with endpoint specified\n");

		return -EINVAL;

	}



	ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",

	ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",

				     &dsi->burst_clk_rate);

	if (ret < 0)

		goto end;

		return ret;



	ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",

	ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",

				     &dsi->esc_clk_rate);

	if (ret < 0)

		goto end;



	of_node_put(ep);

		return ret;



	dsi->bridge_node = of_graph_get_remote_node(node, DSI_PORT_OUT, 0);

	if (!dsi->bridge_node)

		return -EINVAL;



end:

	of_node_put(ep);



	return ret;

	return 0;

}



static int exynos_dsi_bind(struct device *dev, struct device *master,
@@ -1817,6 +1805,10 @@ static int exynos_dsi_probe(struct platform_device *pdev) 


static int exynos_dsi_remove(struct platform_device *pdev)

{

	struct exynos_dsi *dsi = platform_get_drvdata(pdev);



	of_node_put(dsi->bridge_node);



	pm_runtime_disable(&pdev->dev);



	component_del(&pdev->dev, &exynos_dsi_component_ops);

drivers/gpu/drm/i915/gvt/execlist.c

+20 −10
Original line number Diff line number Diff line
@@ -779,8 +779,26 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id) 
	vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;

}



static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_engine_cs *engine;

	struct intel_vgpu_workload *pos, *n;

	unsigned int tmp;



	/* free the unsubmited workloads in the queues. */

	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {

		list_for_each_entry_safe(pos, n,

			&vgpu->workload_q_head[engine->id], list) {

			list_del_init(&pos->list);

			free_workload(pos);

		}

	}

}



void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu)

{

	clean_workloads(vgpu, ALL_ENGINES);

	kmem_cache_destroy(vgpu->workloads);

}
@@ -811,17 +829,9 @@ void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu, 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_engine_cs *engine;

	struct intel_vgpu_workload *pos, *n;

	unsigned int tmp;



	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {

		/* free the unsubmited workload in the queue */

		list_for_each_entry_safe(pos, n,

			&vgpu->workload_q_head[engine->id], list) {

			list_del_init(&pos->list);

			free_workload(pos);

		}



	clean_workloads(vgpu, engine_mask);

	for_each_engine_masked(engine, dev_priv, engine_mask, tmp)

		init_vgpu_execlist(vgpu, engine->id);

}
 
}

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