Commit a359de1b authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+" 



Turned out that the actual bug was in the Memory Controller driver
that programmed shadowed registers without latching the new values
and then there was a bug on EMEM arbitration configuration calculation
that results in a wrong value being latched on resume from suspend.
The Memory Controller has been fixed properly now, hence the workaround
patch could be reverted safely.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 48791f97

arch/arm/mach-tegra/iomap.h

+0 −9
Original line number Original line Diff line number Diff line
@@ -79,24 +79,15 @@ 
#define TEGRA_PMC_BASE			0x7000E400

#define TEGRA_PMC_BASE			0x7000E400

#define TEGRA_PMC_SIZE			SZ_256

#define TEGRA_PMC_SIZE			SZ_256





#define TEGRA_MC_BASE			0x7000F000

#define TEGRA_MC_SIZE			SZ_1K



#define TEGRA_EMC_BASE			0x7000F400

#define TEGRA_EMC_BASE			0x7000F400

#define TEGRA_EMC_SIZE			SZ_1K

#define TEGRA_EMC_SIZE			SZ_1K





#define TEGRA114_MC_BASE		0x70019000

#define TEGRA114_MC_SIZE		SZ_4K



#define TEGRA_EMC0_BASE			0x7001A000

#define TEGRA_EMC0_BASE			0x7001A000

#define TEGRA_EMC0_SIZE			SZ_2K

#define TEGRA_EMC0_SIZE			SZ_2K





#define TEGRA_EMC1_BASE			0x7001A800

#define TEGRA_EMC1_BASE			0x7001A800

#define TEGRA_EMC1_SIZE			SZ_2K

#define TEGRA_EMC1_SIZE			SZ_2K





#define TEGRA124_MC_BASE		0x70019000

#define TEGRA124_MC_SIZE		SZ_4K



#define TEGRA124_EMC_BASE		0x7001B000

#define TEGRA124_EMC_BASE		0x7001B000

#define TEGRA124_EMC_SIZE		SZ_2K

#define TEGRA124_EMC_SIZE		SZ_2K

arch/arm/mach-tegra/sleep-tegra30.S

+0 −21
Original line number Original line Diff line number Diff line
@@ -44,8 +44,6 @@ 
#define EMC_XM2VTTGENPADCTRL		0x310

#define EMC_XM2VTTGENPADCTRL		0x310

#define EMC_XM2VTTGENPADCTRL2		0x314

#define EMC_XM2VTTGENPADCTRL2		0x314





#define MC_EMEM_ARB_CFG			0x90



#define PMC_CTRL			0x0

#define PMC_CTRL			0x0

#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */

#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
@@ -420,22 +418,6 @@ _pll_m_c_x_done: 
	movweq	r0, #:lower16:TEGRA124_EMC_BASE

	movweq	r0, #:lower16:TEGRA124_EMC_BASE

	movteq	r0, #:upper16:TEGRA124_EMC_BASE

	movteq	r0, #:upper16:TEGRA124_EMC_BASE





	cmp	r10, #TEGRA30

	moveq	r2, #0x20

	movweq	r4, #:lower16:TEGRA_MC_BASE

	movteq	r4, #:upper16:TEGRA_MC_BASE

	cmp	r10, #TEGRA114

	moveq	r2, #0x34

	movweq	r4, #:lower16:TEGRA114_MC_BASE

	movteq	r4, #:upper16:TEGRA114_MC_BASE

	cmp	r10, #TEGRA124

	moveq	r2, #0x20

	movweq	r4, #:lower16:TEGRA124_MC_BASE

	movteq	r4, #:upper16:TEGRA124_MC_BASE



	ldr	r1, [r5, r2]		@ restore MC_EMEM_ARB_CFG

	str	r1, [r4, #MC_EMEM_ARB_CFG]



exit_self_refresh:

exit_self_refresh:

	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL

	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL

	str	r1, [r0, #EMC_XM2VTTGENPADCTRL]

	str	r1, [r0, #EMC_XM2VTTGENPADCTRL]
@@ -564,7 +546,6 @@ tegra30_sdram_pad_address: 
	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14

	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c

	.word	TEGRA_MC_BASE + MC_EMEM_ARB_CFG				@0x20

tegra30_sdram_pad_address_end:

tegra30_sdram_pad_address_end:





tegra114_sdram_pad_address:

tegra114_sdram_pad_address:
@@ -581,7 +562,6 @@ tegra114_sdram_pad_address: 
	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28

	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28

	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c

	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c

	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30

	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30

	.word	TEGRA114_MC_BASE + MC_EMEM_ARB_CFG			@0x34

tegra114_sdram_pad_adress_end:

tegra114_sdram_pad_adress_end:





tegra124_sdram_pad_address:

tegra124_sdram_pad_address:
@@ -593,7 +573,6 @@ tegra124_sdram_pad_address: 
	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14

	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c

	.word	TEGRA124_MC_BASE + MC_EMEM_ARB_CFG			@0x20

tegra124_sdram_pad_address_end:

tegra124_sdram_pad_address_end:





tegra30_sdram_pad_size:

tegra30_sdram_pad_size:

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