Commit a315ec7b authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sti-dt-for-v3.20-1' of git://git.stlinux.com/devel/kernel/linux-sti into next/dt 

Merge "STi DT updates for v3.20, round 1" from Maxime Coquelin:

Highlights:
-----------
 - Add USB support for STiH410 & STiH407
 - Add DRM DT nodes for STiH410 & STiH407
 - Add STiH418 SoC support
 - Add DT nodes for MiPHY28lp PHY

* tag 'sti-dt-for-v3.20-1' of git://git.stlinux.com/devel/kernel/linux-sti

:
  ARM: DT: STi: STiH407: Add DT node for MiPHY28lp
  ARM: dts: STiH418: Add B2199 board support
  ARM: dts: Add STiH418 SoC support
  ARM: DT: STiH410: Add DRM dt nodes
  ARM: DT: STiH407: Add DRM dt nodes
  ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb controllers.
  ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
  ARM: STi: DT: STiH407: Add usb2 picophy dt nodes

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 56a9c909 b26373c0

arch/arm/boot/dts/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -504,7 +504,8 @@ dtb-$(CONFIG_ARCH_STI) += \ 
	stih415-b2020.dtb \

	stih416-b2000.dtb \

	stih416-b2020.dtb \

	stih416-b2020e.dtb

	stih416-b2020e.dtb \

	stih418-b2199.dtb

dtb-$(CONFIG_MACH_SUN4I) += \

	sun4i-a10-a1000.dtb \

	sun4i-a10-ba10-tvbox.dtb \

arch/arm/boot/dts/stih407-b2120.dts

+1 −2
Original line number Diff line number Diff line
@@ -7,9 +7,8 @@ 
 * published by the Free Software Foundation.

 */

/dts-v1/;

#include "stih407-clock.dtsi"

#include "stih407-family.dtsi"

#include "stihxxx-b2120.dtsi"

#include "stih407.dtsi"

/ {

	model = "STiH407 B2120";

	compatible = "st,stih407-b2120", "st,stih407";

arch/arm/boot/dts/stih407-family.dtsi

+62 −0
Original line number Diff line number Diff line
@@ -274,5 +274,67 @@ 


			status = "disabled";

		};



		usb2_picophy0: phy1 {

			compatible = "st,stih407-usb2-phy";

			#phy-cells = <0>;

			st,syscfg = <&syscfg_core 0x100 0xf4>;

			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,

				 <&picophyreset STIH407_PICOPHY0_RESET>;

			reset-names = "global", "port";

		};



		miphy28lp_phy: miphy28lp@9b22000 {

			compatible = "st,miphy28lp-phy";

			st,syscfg = <&syscfg_core>;

			#address-cells	= <1>;

			#size-cells	= <1>;

			ranges;



			phy_port0: port@9b22000 {

				reg = <0x9b22000 0xff>,

				      <0x9b09000 0xff>,

				      <0x9b04000 0xff>;

				reg-names = "sata-up",

					    "pcie-up",

					    "pipew";



				st,syscfg = <0x114 0x818 0xe0 0xec>;

				#phy-cells = <1>;



				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY0_SOFTRESET>;

			};



			phy_port1: port@9b2a000 {

				reg = <0x9b2a000 0xff>,

				      <0x9b19000 0xff>,

				      <0x9b14000 0xff>;

				reg-names = "sata-up",

					    "pcie-up",

					    "pipew";



				st,syscfg = <0x118 0x81c 0xe4 0xf0>;



				#phy-cells = <1>;



				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY1_SOFTRESET>;

			};



			phy_port2: port@8f95000 {

				reg = <0x8f95000 0xff>,

				      <0x8f90000 0xff>;

				reg-names = "pipew",

					    "usb3-up";



				st,syscfg = <0x11c 0x820>;



				#phy-cells = <1>;



				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;

			};

		};

	};

};

arch/arm/boot/dts/stih407.dtsi

0 → 100644
+151 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2015 STMicroelectronics Limited.

 * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * publishhed by the Free Software Foundation.

 */

#include "stih407-clock.dtsi"

#include "stih407-family.dtsi"

/ {

	soc {

		/* Display */

		vtg_main: sti-vtg-main@8d02800 {

			compatible = "st,vtg";

			reg = <0x8d02800 0x200>;

			interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;

		};



		vtg_aux: sti-vtg-aux@8d00200 {

			compatible = "st,vtg";

			reg = <0x8d00200 0x100>;

			interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;

		};



		sti-display-subsystem {

			compatible = "st,sti-display-subsystem";

			#address-cells = <1>;

			#size-cells = <1>;



			assigned-clocks	= <&clk_s_d2_quadfs 0>,

					  <&clk_s_d2_quadfs 0>,

					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,

					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,

					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,

					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,

					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,

					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;



			assigned-clock-parents = <0>,

						 <0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>;



			assigned-clock-rates = <297000000>, <297000000>;



			ranges;



			sti-compositor@9d11000 {

				compatible = "st,stih407-compositor";

				reg = <0x9d11000 0x1000>;



				clock-names = "compo_main",

					      "compo_aux",

					      "pix_main",

					      "pix_aux",

					      "pix_gdp1",

					      "pix_gdp2",

					      "pix_gdp3",

					      "pix_gdp4",

					      "main_parent",

					      "aux_parent";



				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,

					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,

					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,

					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,

					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,

					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,

					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,

					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,

					 <&clk_s_d2_quadfs 0>,

					 <&clk_s_d2_quadfs 1>;



				reset-names = "compo-main", "compo-aux";

				resets = <&softreset STIH407_COMPO_SOFTRESET>,

					 <&softreset STIH407_COMPO_SOFTRESET>;

				st,vtg = <&vtg_main>, <&vtg_aux>;

			};



			sti-tvout@8d08000 {

				compatible = "st,stih407-tvout";

				reg = <0x8d08000 0x1000>;

				reg-names = "tvout-reg";

				reset-names = "tvout";

				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;

				#address-cells = <1>;

				#size-cells = <1>;

				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,

						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,

						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,

						  <&clk_s_d0_flexgen CLK_PCM_0>,

						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,

						  <&clk_s_d2_flexgen CLK_HDDAC>;



				assigned-clock-parents = <&clk_s_d2_quadfs 0>,

							 <&clk_tmdsout_hdmi>,

							 <&clk_s_d2_quadfs 0>,

							 <&clk_s_d0_quadfs 0>,

							 <&clk_s_d2_quadfs 0>,

							 <&clk_s_d2_quadfs 0>;

				ranges;



				sti-hdmi@8d04000 {

					compatible = "st,stih407-hdmi";

					reg = <0x8d04000 0x1000>;

					reg-names = "hdmi-reg";

					interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;

					interrupt-names	= "irq";

					clock-names = "pix",

						      "tmds",

						      "phy",

						      "audio",

						      "main_parent",

						      "aux_parent";



					clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,

						 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,

						 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,

						 <&clk_s_d0_flexgen CLK_PCM_0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 1>;



					hdmi,hpd-gpio = <&pio5 3>;

					reset-names = "hdmi";

					resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;

					ddc = <&hdmiddc>;



				};



				sti-hda@8d02000 {

					compatible = "st,stih407-hda";

					reg = <0x8d02000 0x400>, <0x92b0120 0x4>;

					reg-names = "hda-reg", "video-dacs-ctrl";

					clock-names = "pix",

						      "hddac",

						      "main_parent",

						      "aux_parent";

					clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,

						 <&clk_s_d2_flexgen CLK_HDDAC>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 1>;

				};

			};

		};

	};

};

arch/arm/boot/dts/stih410.dtsi

+208 −0
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@@ -10,5 +10,213 @@ 
#include "stih407-family.dtsi"

#include "stih410-pinctrl.dtsi"

/ {

	soc {

		usb2_picophy1: phy2 {

			compatible = "st,stih407-usb2-phy";

			#phy-cells = <0>;

			st,syscfg = <&syscfg_core 0xf8 0xf4>;

			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,

				 <&picophyreset STIH407_PICOPHY0_RESET>;

			reset-names = "global", "port";

		};



		usb2_picophy2: phy3 {

			compatible = "st,stih407-usb2-phy";

			#phy-cells = <0>;

			st,syscfg = <&syscfg_core 0xfc 0xf4>;

			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,

				 <&picophyreset STIH407_PICOPHY1_RESET>;

			reset-names = "global", "port";

		};



		ohci0: usb@9a03c00 {

			compatible = "st,st-ohci-300x";

			reg = <0x9a03c00 0x100>;

			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;

			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;

			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,

				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;

			reset-names = "power", "softreset";

			phys = <&usb2_picophy1>;

			phy-names = "usb";

		};



		ehci0: usb@9a03e00 {

			compatible = "st,st-ehci-300x";

			reg = <0x9a03e00 0x100>;

			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb0>;

			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;

			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,

				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;

			reset-names = "power", "softreset";

			phys = <&usb2_picophy1>;

			phy-names = "usb";

		};



		ohci1: usb@9a83c00 {

			compatible = "st,st-ohci-300x";

			reg = <0x9a83c00 0x100>;

			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;

			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;

			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,

				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;

			reset-names = "power", "softreset";

			phys = <&usb2_picophy2>;

			phy-names = "usb";

		};



		ehci1: usb@9a83e00 {

			compatible = "st,st-ehci-300x";

			reg = <0x9a83e00 0x100>;

			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb1>;

			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;

			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,

				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;

			reset-names = "power", "softreset";

			phys = <&usb2_picophy2>;

			phy-names = "usb";

		};



		/* Display */

		vtg_main: sti-vtg-main@8d02800 {

			compatible = "st,vtg";

			reg = <0x8d02800 0x200>;

			interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;

		};



		vtg_aux: sti-vtg-aux@8d00200 {

			compatible = "st,vtg";

			reg = <0x8d00200 0x100>;

			interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;

		};



		sti-display-subsystem {

			compatible = "st,sti-display-subsystem";

			#address-cells = <1>;

			#size-cells = <1>;



			assigned-clocks	= <&clk_s_d2_quadfs 0>,

					  <&clk_s_d2_quadfs 0>,

					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,

					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,

					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,

					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,

					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,

					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;



			assigned-clock-parents = <0>,

						 <0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 0>;



			assigned-clock-rates = <297000000>, <297000000>;



			ranges;



			sti-compositor@9d11000 {

				compatible = "st,stih407-compositor";

				reg = <0x9d11000 0x1000>;



				clock-names = "compo_main",

					      "compo_aux",

					      "pix_main",

					      "pix_aux",

					      "pix_gdp1",

					      "pix_gdp2",

					      "pix_gdp3",

					      "pix_gdp4",

					      "main_parent",

					      "aux_parent";



				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,

					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,

					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,

					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,

					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,

					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,

					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,

					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,

					 <&clk_s_d2_quadfs 0>,

					 <&clk_s_d2_quadfs 1>;



				reset-names = "compo-main", "compo-aux";

				resets = <&softreset STIH407_COMPO_SOFTRESET>,

					 <&softreset STIH407_COMPO_SOFTRESET>;

				st,vtg = <&vtg_main>, <&vtg_aux>;

			};



			sti-tvout@8d08000 {

				compatible = "st,stih407-tvout";

				reg = <0x8d08000 0x1000>;

				reg-names = "tvout-reg";

				reset-names = "tvout";

				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;

				#address-cells = <1>;

				#size-cells = <1>;

				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,

						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,

						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,

						  <&clk_s_d0_flexgen CLK_PCM_0>,

						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,

						  <&clk_s_d2_flexgen CLK_HDDAC>;



				assigned-clock-parents = <&clk_s_d2_quadfs 0>,

							 <&clk_tmdsout_hdmi>,

							 <&clk_s_d2_quadfs 0>,

							 <&clk_s_d0_quadfs 0>,

							 <&clk_s_d2_quadfs 0>,

							 <&clk_s_d2_quadfs 0>;

				ranges;



				sti-hdmi@8d04000 {

					compatible = "st,stih407-hdmi";

					reg = <0x8d04000 0x1000>;

					reg-names = "hdmi-reg";

					interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;

					interrupt-names	= "irq";

					clock-names = "pix",

						      "tmds",

						      "phy",

						      "audio",

						      "main_parent",

						      "aux_parent";



					clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,

						 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,

						 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,

						 <&clk_s_d0_flexgen CLK_PCM_0>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 1>;



					hdmi,hpd-gpio = <&pio5 3>;

					reset-names = "hdmi";

					resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;

					ddc = <&hdmiddc>;



				};



				sti-hda@8d02000 {

					compatible = "st,stih407-hda";

					reg = <0x8d02000 0x400>, <0x92b0120 0x4>;

					reg-names = "hda-reg", "video-dacs-ctrl";

					clock-names = "pix",

						      "hddac",

						      "main_parent",

						      "aux_parent";

					clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,

						 <&clk_s_d2_flexgen CLK_HDDAC>,

						 <&clk_s_d2_quadfs 0>,

						 <&clk_s_d2_quadfs 1>;

				};

			};

		};

	};

};

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