Merge tag 'renesas-soc-for-v4.7' of... (a3003158) · Commits · 戴 / test

arch/arm/boot/dts/r8a7791-koelsch.dts

+1 −0

Original line number	Diff line number	Diff line
		@@ -661,6 +661,7 @@
		};

		&pcie_bus_clk {
		clock-frequency = <100000000>;
		status = "okay";
		};

arch/arm/boot/dts/r8a7791-porter.dts

+1 −13

Original line number	Diff line number	Diff line
		@@ -143,19 +143,11 @@
		};

		&pfc {
		pinctrl-0 = <&scif_clk_pins>;
		pinctrl-names = "default";

		scif0_pins: serial0 {
		renesas,groups = "scif0_data_d";
		renesas,function = "scif0";
		};

		scif_clk_pins: scif_clk {
		renesas,groups = "scif_clk";
		renesas,function = "scif_clk";
		};

		ether_pins: ether {
		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
		renesas,function = "eth";
		@@ -229,11 +221,6 @@
		status = "okay";
		};

		&scif_clk {
		clock-frequency = <14745600>;
		status = "okay";
		};

		&ether {
		pinctrl-0 = <&ether_pins &phy1_pins>;
		pinctrl-names = "default";
		@@ -414,6 +401,7 @@
		};

		&pcie_bus_clk {
		clock-frequency = <100000000>;
		status = "okay";
		};

arch/arm/boot/dts/r8a7791.dtsi

+1 −4

Original line number	Diff line number	Diff line
		@@ -1083,9 +1083,8 @@
		pcie_bus_clk: pcie_bus_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-frequency = <0>;
		clock-output-names = "pcie_bus";
		status = "disabled";
		};

		/* External SCIF clock */
		@@ -1094,7 +1093,6 @@
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
		status = "disabled";
		};

		/* External USB clock - can be overridden by the board */
		@@ -1112,7 +1110,6 @@
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
		clock-output-names = "can_clk";
		status = "disabled";
		};

		/* Special CPG clocks */

arch/arm/mach-shmobile/timer.c

+19 −37

Original line number	Diff line number	Diff line
		@@ -20,29 +20,9 @@

		#include "common.h"

		static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
		unsigned int mult, unsigned int div)
		{
		/* calculate a worst-case loops-per-jiffy value
		* based on maximum cpu core hz setting and the
		* __delay() implementation in arch/arm/lib/delay.S
		*
		* this will result in a longer delay than expected
		* when the cpu core runs on lower frequencies.
		*/

		unsigned int value = HZ * div / mult;

		if (!preset_lpj)
		preset_lpj = max_cpu_core_hz / value;
		}

		void __init shmobile_init_delay(void)
		{
		struct device_node np, cpus;
		bool is_a7_a8_a9 = false;
		bool is_a15 = false;
		bool has_arch_timer = false;
		u32 max_freq = 0;

		cpus = of_find_node_by_path("/cpus");
		@@ -52,19 +32,16 @@ void __init shmobile_init_delay(void)
		for_each_child_of_node(cpus, np) {
		u32 freq;

		if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER) &&
		(of_device_is_compatible(np, "arm,cortex-a7") \|\|
		of_device_is_compatible(np, "arm,cortex-a15"))) {
		of_node_put(np);
		of_node_put(cpus);
		return;
		}

		if (!of_property_read_u32(np, "clock-frequency", &freq))
		max_freq = max(max_freq, freq);

		if (of_device_is_compatible(np, "arm,cortex-a8") \|\|
		of_device_is_compatible(np, "arm,cortex-a9")) {
		is_a7_a8_a9 = true;
		} else if (of_device_is_compatible(np, "arm,cortex-a7")) {
		is_a7_a8_a9 = true;
		has_arch_timer = true;
		} else if (of_device_is_compatible(np, "arm,cortex-a15")) {
		is_a15 = true;
		has_arch_timer = true;
		}
		}

		of_node_put(cpus);
		@@ -72,10 +49,15 @@ void __init shmobile_init_delay(void)
		if (!max_freq)
		return;

		if (!has_arch_timer \|\| !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
		if (is_a7_a8_a9)
		shmobile_setup_delay_hz(max_freq, 1, 3);
		else if (is_a15)
		shmobile_setup_delay_hz(max_freq, 2, 4);
		}
		/*
		* Calculate a worst-case loops-per-jiffy value
		* based on maximum cpu core hz setting and the
		* __delay() implementation in arch/arm/lib/delay.S.
		*
		* This will result in a longer delay than expected
		* when the cpu core runs on lower frequencies.
		*/

		if (!preset_lpj)
		preset_lpj = max_freq / HZ;
		}

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