Commit a2efd681 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-mediatek' into next 

* pci/host-mediatek:
  PCI: mediatek: Use PCI_NUM_INTX
  PCI: mediatek: Add MSI support for MT2712 and MT7622
  PCI: mediatek: Use bus->sysdata to get host private data
  dt-bindings: PCI: Add support for MT2712 and MT7622
  PCI: mediatek: Add controller support for MT2712 and MT7622
  dt-bindings: PCI: Cleanup MediaTek binding text
  dt-bindings: PCI: Rename MediaTek binding
  PCI: mediatek: Switch to use platform_get_resource_byname()
  PCI: mediatek: Add a structure to abstract the controller generations
  PCI: mediatek: Rename port->index and mtk_pcie_parse_ports()
  PCI: mediatek: Use readl_poll_timeout() to wait for Gen2 training
  PCI: mediatek: Explicitly request exclusive reset control
parents 9857f125 d84c246b

Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt→Documentation/devicetree/bindings/pci/mediatek-pcie.txt

+176 −22
Original line number Diff line number Diff line 
MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs



PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root

ports supports a Gen2 1-lane Link and has PIPE interface to PHY.

MediaTek Gen2 PCIe controller



Required properties:

- compatible: Should contain "mediatek,mt7623-pcie".

- compatible: Should contain one of the following strings:

	"mediatek,mt2701-pcie"

	"mediatek,mt2712-pcie"

	"mediatek,mt7622-pcie"

	"mediatek,mt7623-pcie"

- device_type: Must be "pci"

- reg: Base addresses and lengths of the PCIe controller.

- reg: Base addresses and lengths of the PCIe subsys and root ports.

- reg-names: Names of the above areas to use during resource lookup.

- #address-cells: Address representation for root ports (must be 3)

- #size-cells: Size representation for root ports (must be 2)

- #interrupt-cells: Size representation for interrupts (must be 1)

- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties

  Please refer to the standard PCI bus binding document for a more detailed

  explanation.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

- clock-names:

  Mandatory entries:

   - sys_ckN :transaction layer and data link layer clock

  Required entries for MT2701/MT7623:

   - free_ck :for reference clock of PCIe subsys

  - sys_ck0 :for clock of Port0

  - sys_ck1 :for clock of Port1

  - sys_ck2 :for clock of Port2

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

  - pcie-rst0 :port0 reset

  - pcie-rst1 :port1 reset

  - pcie-rst2 :port2 reset

  Required entries for MT2712/MT7622:

   - ahb_ckN :AHB slave interface operating clock for CSR access and RC

	      initiated MMIO access

  Required entries for MT7622:

   - axi_ckN :application layer MMIO channel operating clock

   - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when

	      pcie_mac_ck/pcie_pipe_ck is turned off

   - obff_ckN :OBFF functional block operating clock

   - pipe_ckN :LTSSM and PHY/MAC layer operating clock

  where N starting from 0 to one less than the number of root ports.

- phys: List of PHY specifiers (used by generic PHY framework).

- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the

  number of PHYs as specified in *phys* property.
@@ -34,6 +36,20 @@ Required properties: 
- bus-range: Range of bus numbers associated with this controller.

- ranges: Ranges for the PCI memory and I/O regions.



Required properties for MT7623/MT2701:

- #interrupt-cells: Size representation for interrupts (must be 1)

- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties

  Please refer to the standard PCI bus binding document for a more detailed

  explanation.

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the

  number of root ports.



Required properties for MT2712/MT7622:

-interrupts: A list of interrupt outputs of the controller, must have one

	     entry for each PCIe port



In addition, the device tree node must have sub-nodes describing each

PCIe port interface, having the following mandatory properties:
@@ -51,7 +67,7 @@ Required properties: 
  property is sufficient.

- num-lanes: Number of lanes to use for this port.



Examples:

Examples for MT7623:



	hifsys: syscon@1a000000 {

		compatible = "mediatek,mt7623-hifsys",
@@ -69,6 +85,7 @@ Examples: 
		      <0 0x1a142000 0 0x1000>, /* Port0 registers */

		      <0 0x1a143000 0 0x1000>, /* Port1 registers */

		      <0 0x1a144000 0 0x1000>; /* Port2 registers */

		reg-names = "subsys", "port0", "port1", "port2";

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;
@@ -85,7 +102,8 @@ Examples: 
			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,

			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;

		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";

		phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;

		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,

		       <&pcie2_phy PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

		bus-range = <0x00 0xff>;
@@ -128,3 +146,139 @@ Examples: 
			num-lanes = <1>;

		};

	};



Examples for MT2712:

	pcie: pcie@11700000 {

		compatible = "mediatek,mt2712-pcie";

		device_type = "pci";

		reg = <0 0x11700000 0 0x1000>,

		      <0 0x112ff000 0 0x1000>;

		reg-names = "port0", "port1";

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,

			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,

			 <&pericfg CLK_PERI_PCIE0>,

			 <&pericfg CLK_PERI_PCIE1>;

		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";

		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0", "pcie-phy1";

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;



		pcie0: pcie@0,0 {

			device_type = "pci";

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges;

			num-lanes = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc0 0>,

					<0 0 0 2 &pcie_intc0 1>,

					<0 0 0 3 &pcie_intc0 2>,

					<0 0 0 4 &pcie_intc0 3>;

			pcie_intc0: interrupt-controller {

				interrupt-controller;

				#address-cells = <0>;

				#interrupt-cells = <1>;

			};

		};



		pcie1: pcie@1,0 {

			device_type = "pci";

			reg = <0x0800 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges;

			num-lanes = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc1 0>,

					<0 0 0 2 &pcie_intc1 1>,

					<0 0 0 3 &pcie_intc1 2>,

					<0 0 0 4 &pcie_intc1 3>;

			pcie_intc1: interrupt-controller {

				interrupt-controller;

				#address-cells = <0>;

				#interrupt-cells = <1>;

			};

		};

	};



Examples for MT7622:

	pcie: pcie@1a140000 {

		compatible = "mediatek,mt7622-pcie";

		device_type = "pci";

		reg = <0 0x1a140000 0 0x1000>,

		      <0 0x1a143000 0 0x1000>,

		      <0 0x1a145000 0 0x1000>;

		reg-names = "subsys", "port0", "port1";

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,

			 <&pciesys CLK_PCIE_P1_MAC_EN>,

			 <&pciesys CLK_PCIE_P0_AHB_EN>,

			 <&pciesys CLK_PCIE_P1_AHB_EN>,

			 <&pciesys CLK_PCIE_P0_AUX_EN>,

			 <&pciesys CLK_PCIE_P1_AUX_EN>,

			 <&pciesys CLK_PCIE_P0_AXI_EN>,

			 <&pciesys CLK_PCIE_P1_AXI_EN>,

			 <&pciesys CLK_PCIE_P0_OBFF_EN>,

			 <&pciesys CLK_PCIE_P1_OBFF_EN>,

			 <&pciesys CLK_PCIE_P0_PIPE_EN>,

			 <&pciesys CLK_PCIE_P1_PIPE_EN>;

		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",

			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",

			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";

		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0", "pcie-phy1";

		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;



		pcie0: pcie@0,0 {

			device_type = "pci";

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges;

			num-lanes = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc0 0>,

					<0 0 0 2 &pcie_intc0 1>,

					<0 0 0 3 &pcie_intc0 2>,

					<0 0 0 4 &pcie_intc0 3>;

			pcie_intc0: interrupt-controller {

				interrupt-controller;

				#address-cells = <0>;

				#interrupt-cells = <1>;

			};

		};



		pcie1: pcie@1,0 {

			device_type = "pci";

			reg = <0x0800 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges;

			num-lanes = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc1 0>,

					<0 0 0 2 &pcie_intc1 1>,

					<0 0 0 3 &pcie_intc1 2>,

					<0 0 0 4 &pcie_intc1 3>;

			pcie_intc1: interrupt-controller {

				interrupt-controller;

				#address-cells = <0>;

				#interrupt-cells = <1>;

			};

		};

	};

drivers/pci/host/Kconfig

+2 −3
Original line number Diff line number Diff line
@@ -182,14 +182,13 @@ config PCIE_ROCKCHIP 


config PCIE_MEDIATEK

	bool "MediaTek PCIe controller"

	depends on ARM && (ARCH_MEDIATEK || COMPILE_TEST)

	depends on (ARM || ARM64) && (ARCH_MEDIATEK || COMPILE_TEST)

	depends on OF

	depends on PCI

	select PCIEPORTBUS

	help

	  Say Y here if you want to enable PCIe controller support on

	  MT7623 series SoCs.  There is one single root complex with 3 root

	  ports available.  Each port supports Gen2 lane x1.

	  MediaTek SoCs.



config PCIE_TANGO_SMP8759

	bool "Tango SMP8759 PCIe controller (DANGEROUS)"

drivers/pci/host/pcie-mediatek.c

+689 −67

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