Commit a2edaf78 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx8mq-4.21' of... 

Merge tag 'imx8mq-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late

i.MX8MQ device tree support for 4.21:
 - It contains the initial device tree support for i.MX8MQ - the first
   ARM64 i.MX processor.  It features a quad Cortex-A53 core that
   operates at speeds of up to 1.3 GHz, a Cortex-M4 core for
   low-power processing, a DRAM controller that supports 32-bit/16-bit
   LPDDR4/DDR4/DDR3L memory, and hardware acceleration for 4K video
   playback.
 - A couple of patches from Baruch that add watchdog device for i.MX8MQ
   enable it for imx8mq-evk board.

* tag 'imx8mq-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  arm64: dts: imx8mq-evk: enable watchdog
  arm64: dts: imx8mq: add watchdog devices
  MAINTAINERS: add i.MX8 DT path to i.MX architecture
  arm64: add support for i.MX8M EVK board
  arm64: add basic DTS for i.MX8MQ
  arm64: add basic Kconfig symbols for i.MX8
  arm64: dts: ls1046a: add qdma device tree nodes
  arm64: dts: ls1043a: add qdma device tree nodes
  arm64: dts: ls1088a: Add missing dma-ranges property
  arm64: dts: ls1088a: Move fsl-mc node
  arm64: dts: fsl: Add all CPUs in cooling maps
  arm64: dts: Add support for NXP LS1028A SoC
  arm64: dts: layerscape: removed compatible string "snps,dw-pcie"
  arm64: dts: fsl: Add the status property disable PCIe
  arm64: dts: ls1012a: Add FRWY-LS1012A board support
  dt-bindings: Add binding for i.MX8MQ CCM
  arm64: dts: add LX2160AQDS board support
  arm64: dts: add LX2160ARDB board support
  arm64: dts: add QorIQ LX2160A SoC support

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 5e0bd98f 3bbc9abb

Documentation/devicetree/bindings/clock/imx8mq-clock.txt

0 → 100644
+20 −0
Original line number Diff line number Diff line 
* Clock bindings for NXP i.MX8M Quad



Required properties:

- compatible: Should be "fsl,imx8mq-ccm"

- reg: Address and length of the register set

- #clock-cells: Should be <1>

- clocks: list of clock specifiers, must contain an entry for each required

          entry in clock-names

- clock-names: should include the following entries:

    - "ckil"

    - "osc_25m"

    - "osc_27m"

    - "clk_ext1"

    - "clk_ext2"

    - "clk_ext3"

    - "clk_ext4"



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx8mq-clock.h

for the full list of i.MX8M Quad clock IDs.

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1523,6 +1523,7 @@ F: arch/arm/mach-imx/ 
F:	arch/arm/mach-mxs/

F:	arch/arm/boot/dts/imx*

F:	arch/arm/configs/imx*_defconfig

F:	arch/arm64/boot/dts/freescale/imx*

F:	drivers/clk/imx/

F:	drivers/firmware/imx/

F:	drivers/soc/imx/

arch/arm64/Kconfig.platforms

+8 −0
Original line number Diff line number Diff line
@@ -142,6 +142,14 @@ config ARCH_MVEBU 
	   - Armada 7K SoC Family

	   - Armada 8K SoC Family



config ARCH_MXC

	bool "ARMv8 based NXP i.MX SoC family"

	select ARM64_ERRATUM_843419

	select ARM64_ERRATUM_845719

	help

	  This enables support for the ARMv8 based SoCs in the

	  NXP i.MX family.



config ARCH_QCOM

	bool "Qualcomm Platforms"

	select GPIOLIB

arch/arm64/boot/dts/freescale/Makefile

+7 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
@@ -13,3 +16,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb 
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb



dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb

arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts

0 → 100644
+25 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree file for Freescale LS1012A FRWY Board.

 *

 * Copyright 2018 NXP

 *

 * Pramod Kumar <pramod.kumar_1@nxp.com>

 *

 */

/dts-v1/;



#include "fsl-ls1012a.dtsi"



/ {

	model = "LS1012A FRWY Board";

	compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";

};



&duart0 {

	status = "okay";

};



&i2c0 {

	status = "okay";

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE