Commit a2e7699e authored by Tomer Tayar's avatar Tomer Tayar Committed by David S. Miller
Browse files

qed*: Refactoring and rearranging FW API with no functional impact 



This patch refactors and reorders the FW API files in preparation of
upgrading the code to support new FW.

- Make use of the BIT macro in appropriate places.
- Whitespace changes to align values and code blocks.
- Comments are updated (spelling mistakes, removed if not clear).
- Group together code blocks which are related or deal with similar
 matters.

Signed-off-by: default avatarAriel Elior <Ariel.Elior@cavium.com>
Signed-off-by: default avatarMichal Kalderon <Michal.Kalderon@cavium.com>
Signed-off-by: default avatarTomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bbb6189d

drivers/infiniband/hw/qedr/qedr_hsi_rdma.h

+54 −54
Original line number Diff line number Diff line
@@ -494,7 +494,7 @@ struct rdma_sq_fmr_wqe { 
#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT		6

#define RDMA_SQ_FMR_WQE_RESERVED4_MASK			0x1FF

#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT			7

	__le32 Reserved5;

	__le32 reserved5;

};



/* First element (16 bytes) of fmr wqe */
@@ -574,7 +574,7 @@ struct rdma_sq_fmr_wqe_3rd { 
#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT			6

#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK			0x1FF

#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_SHIFT			7

	__le32 Reserved5;

	__le32 reserved5;

};



struct rdma_sq_local_inv_wqe {

drivers/net/ethernet/qlogic/qed/qed_cxt.c

+3 −3
Original line number Diff line number Diff line
@@ -110,7 +110,7 @@ struct src_ent { 
};



#define CDUT_SEG_ALIGNMET		3 /* in 4k chunks */

#define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))

#define CDUT_SEG_ALIGNMET_IN_BYTES	BIT(CDUT_SEG_ALIGNMET + 12)



#define CONN_CXT_SIZE(p_hwfn) \

	ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
@@ -2326,7 +2326,7 @@ qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, 
		for (elem_i = 0; elem_i < elems_per_p; elem_i++) {

			elem = (union type1_task_context *)elem_start;

			SET_FIELD(elem->roce_ctx.tdif_context.flags1,

				  TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);

				  TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf);

			elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);

		}

	}

drivers/net/ethernet/qlogic/qed/qed_debug.c

+43 −59
Original line number Diff line number Diff line
@@ -358,20 +358,14 @@ struct phy_defs { 
			(arr)[i] = qed_rd(dev, ptt, addr); \

	} while (0)



#ifndef DWORDS_TO_BYTES

#define DWORDS_TO_BYTES(dwords)		((dwords) * BYTES_IN_DWORD)

#endif

#ifndef BYTES_TO_DWORDS

#define BYTES_TO_DWORDS(bytes)		((bytes) / BYTES_IN_DWORD)

#endif



/* extra lines include a signature line + optional latency events line */

#ifndef NUM_DBG_LINES

/* Extra lines include a signature line + optional latency events line */

#define NUM_EXTRA_DBG_LINES(block_desc) \

	(1 + ((block_desc)->has_latency_events ? 1 : 0))

#define NUM_DBG_LINES(block_desc) \

	((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))

#endif



#define RAM_LINES_TO_DWORDS(lines)	((lines) * 2)

#define RAM_LINES_TO_BYTES(lines) \
@@ -441,23 +435,17 @@ struct phy_defs { 


#define FW_IMG_MAIN			1



#ifndef REG_FIFO_ELEMENT_DWORDS

#define REG_FIFO_ELEMENT_DWORDS		2

#endif

#define REG_FIFO_DEPTH_ELEMENTS		32

#define REG_FIFO_DEPTH_DWORDS \

	(REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS)



#ifndef IGU_FIFO_ELEMENT_DWORDS

#define IGU_FIFO_ELEMENT_DWORDS		4

#endif

#define IGU_FIFO_DEPTH_ELEMENTS		64

#define IGU_FIFO_DEPTH_DWORDS \

	(IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS)



#ifndef PROTECTION_OVERRIDE_ELEMENT_DWORDS

#define PROTECTION_OVERRIDE_ELEMENT_DWORDS	2

#endif

#define PROTECTION_OVERRIDE_DEPTH_ELEMENTS	20

#define PROTECTION_OVERRIDE_DEPTH_DWORDS \

	(PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \
@@ -1089,6 +1077,20 @@ static struct block_defs block_xyld_defs = { 
	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12

};



static struct block_defs block_ptld_defs = {

	"ptld", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_ypld_defs = {

	"ypld", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_prm_defs = {

	"prm",

	{true, true}, false, 0,
@@ -1221,6 +1223,34 @@ static struct block_defs block_cau_defs = { 
	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19

};



static struct block_defs block_rgfs_defs = {

	"rgfs", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_rgsrc_defs = {

	"rgsrc", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_tgfs_defs = {

	"tgfs", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_tgsrc_defs = {

	"tgsrc", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_umac_defs = {

	"umac",

	{false, true}, false, 0,
@@ -1338,48 +1368,6 @@ static struct block_defs block_avs_wrap_defs = { 
	true, false, DBG_RESET_REG_MISCS_PL_UA, 11

};



static struct block_defs block_rgfs_defs = {

	"rgfs", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_rgsrc_defs = {

	"rgsrc", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_tgfs_defs = {

	"tgfs", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_tgsrc_defs = {

	"tgsrc", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_ptld_defs = {

	"ptld", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_ypld_defs = {

	"ypld", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},

	0, 0, 0, 0, 0,

	false, false, MAX_DBG_RESET_REGS, 0

};



static struct block_defs block_misc_aeu_defs = {

	"misc_aeu", {false, false}, false, 0,

	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
@@ -5596,10 +5584,6 @@ struct igu_fifo_addr_data { 


#define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR	4



/********************************* Macros ************************************/



#define BYTES_TO_DWORDS(bytes)			((bytes) / BYTES_IN_DWORD)



/***************************** Constant Arrays *******************************/



struct user_dbg_array {

drivers/net/ethernet/qlogic/qed/qed_dev.c

+2 −2
Original line number Diff line number Diff line
@@ -758,7 +758,7 @@ static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 
/* This function reconfigures the QM pf on the fly.

 * For this purpose we:

 * 1. reconfigure the QM database

 * 2. set new values to runtime arrat

 * 2. set new values to runtime array

 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM

 * 4. activate init tool in QM_PF stage

 * 5. send an sdm_qm_cmd through rbc interface to release the QM
@@ -1515,7 +1515,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 
			     NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);

	}



	/* Protocl Configuration  */

	/* Protocol Configuration */

	STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,

		     (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);

	STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+3999 −3696

File changed.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE