Commit a2e164e7 authored by Vitaly Kuznetsov's avatar Vitaly Kuznetsov Committed by Paolo Bonzini
Browse files

x86/kvm/hyper-v: add reenlightenment MSRs support 



Nested Hyper-V/Windows guest running on top of KVM will use TSC page
clocksource in two cases:
- L0 exposes invariant TSC (CPUID.80000007H:EDX[8]).
- L0 provides Hyper-V Reenlightenment support (CPUID.40000003H:EAX[13]).

Exposing invariant TSC effectively blocks migration to hosts with different
TSC frequencies, providing reenlightenment support will be needed when we
start migrating nested workloads.

Implement rudimentary support for reenlightenment MSRs. For now, these are
just read/write MSRs with no effect.

Signed-off-by: default avatarVitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: default avatarRoman Kagan <rkagan@virtuozzo.com>
Signed-off-by: default avatarRadim Krčmář <rkrcmar@redhat.com>
parent ddd6f0e9

arch/x86/include/asm/kvm_host.h

+4 −0
Original line number Diff line number Diff line
@@ -756,6 +756,10 @@ struct kvm_hv { 
	HV_REFERENCE_TSC_PAGE tsc_ref;



	struct idr conn_to_evt;



	u64 hv_reenlightenment_control;

	u64 hv_tsc_emulation_control;

	u64 hv_tsc_emulation_status;

};



enum kvm_irqchip_mode {

arch/x86/kvm/hyperv.c

+21 −0
Original line number Diff line number Diff line
@@ -737,6 +737,9 @@ static bool kvm_hv_msr_partition_wide(u32 msr) 
	case HV_X64_MSR_CRASH_CTL:

	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:

	case HV_X64_MSR_RESET:

	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:

	case HV_X64_MSR_TSC_EMULATION_CONTROL:

	case HV_X64_MSR_TSC_EMULATION_STATUS:

		r = true;

		break;

	}
@@ -982,6 +985,15 @@ static int kvm_hv_set_msr_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data, 
			kvm_make_request(KVM_REQ_HV_RESET, vcpu);

		}

		break;

	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:

		hv->hv_reenlightenment_control = data;

		break;

	case HV_X64_MSR_TSC_EMULATION_CONTROL:

		hv->hv_tsc_emulation_control = data;

		break;

	case HV_X64_MSR_TSC_EMULATION_STATUS:

		hv->hv_tsc_emulation_status = data;

		break;

	default:

		vcpu_unimpl(vcpu, "Hyper-V uhandled wrmsr: 0x%x data 0x%llx\n",

			    msr, data);
@@ -1106,6 +1118,15 @@ static int kvm_hv_get_msr_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 
	case HV_X64_MSR_RESET:

		data = 0;

		break;

	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:

		data = hv->hv_reenlightenment_control;

		break;

	case HV_X64_MSR_TSC_EMULATION_CONTROL:

		data = hv->hv_tsc_emulation_control;

		break;

	case HV_X64_MSR_TSC_EMULATION_STATUS:

		data = hv->hv_tsc_emulation_status;

		break;

	default:

		vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);

		return 1;

arch/x86/kvm/x86.c

+11 −1
Original line number Diff line number Diff line
@@ -1034,7 +1034,11 @@ static u32 emulated_msrs[] = { 
	HV_X64_MSR_VP_RUNTIME,

	HV_X64_MSR_SCONTROL,

	HV_X64_MSR_STIMER0_CONFIG,

	HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,

	HV_X64_MSR_APIC_ASSIST_PAGE,

	HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,

	HV_X64_MSR_TSC_EMULATION_STATUS,



	MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,

	MSR_KVM_PV_EOI_EN,



	MSR_IA32_TSC_ADJUST,
@@ -2453,6 +2457,9 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:

	case HV_X64_MSR_CRASH_CTL:

	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:

	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:

	case HV_X64_MSR_TSC_EMULATION_CONTROL:

	case HV_X64_MSR_TSC_EMULATION_STATUS:

		return kvm_hv_set_msr_common(vcpu, msr, data,

					     msr_info->host_initiated);

	case MSR_IA32_BBL_CR_CTL3:
@@ -2683,6 +2690,9 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:

	case HV_X64_MSR_CRASH_CTL:

	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:

	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:

	case HV_X64_MSR_TSC_EMULATION_CONTROL:

	case HV_X64_MSR_TSC_EMULATION_STATUS:

		return kvm_hv_get_msr_common(vcpu,

					     msr_info->index, &msr_info->data);

		break;

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