Merge tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drm (a2d635de) · Commits · 戴 / test

Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt

+4 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,7 @@ Required properties:
		- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
		- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
		followed by the common "amlogic,meson-gx-dw-hdmi"
		- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-dw-hdmi"
		- reg: Physical base address and length of the controller's registers.
		- interrupts: The HDMI interrupt number
		- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
		@@ -66,6 +67,9 @@ corresponding to each HDMI output and input.
		S905X (GXL) VENC Input TMDS Output
		S905D (GXL) VENC Input TMDS Output
		S912 (GXM) VENC Input TMDS Output
		S905X2 (G12A) VENC Input TMDS Output
		S905Y2 (G12A) VENC Input TMDS Output
		S905D2 (G12A) VENC Input TMDS Output

		Example:

Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt

+6 −3

Original line number	Diff line number	Diff line
		@@ -57,18 +57,18 @@ Required properties:
		- GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
		- GXM (S912) : "amlogic,meson-gxm-vpu"
		followed by the common "amlogic,meson-gx-vpu"
		- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-vpu"
		- reg: base address and size of he following memory-mapped regions :
		- vpu
		- hhi
		- dmc
		- reg-names: should contain the names of the previous memory regions
		- interrupts: should contain the VENC Vsync interrupt number
		- amlogic,canvas: phandle to canvas provider node as described in the file
		../soc/amlogic/amlogic,canvas.txt

		Optional properties:
		- power-domains: Optional phandle to associated power domain as described in
		the file ../power/power_domain.txt
		- amlogic,canvas: phandle to canvas provider node as described in the file
		../soc/amlogic/amlogic,canvas.txt

		Required nodes:

		@@ -84,6 +84,9 @@ corresponding to each VPU output.
		S905X (GXL) CVBS VDAC HDMI-TX
		S905D (GXL) CVBS VDAC HDMI-TX
		S912 (GXM) CVBS VDAC HDMI-TX
		S905X2 (G12A) CVBS VDAC HDMI-TX
		S905Y2 (G12A) CVBS VDAC HDMI-TX
		S905D2 (G12A) CVBS VDAC HDMI-TX

		Example:

Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt

+26 −6

Original line number	Diff line number	Diff line
		@@ -6,15 +6,32 @@ Required properties:

		Optional properties:
		- powerdown-gpios: power-down gpio
		- reg: I2C address. If and only if present the device node
		should be placed into the i2c controller node where the
		tfp410 i2c is connected to.
		- reg: I2C address. If and only if present the device node should be placed
		into the I2C controller node where the TFP410 I2C is connected to.
		- ti,deskew: data de-skew in 350ps increments, from -4 to +3, as configured
		through th DK[3:1] pins. This property shall be present only if the TFP410
		is not connected through I2C.

		Required nodes:
		- Video port 0 for DPI input [1].
		- Video port 1 for DVI output [1].

		[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
		This device has two video ports. Their connections are modeled using the OF
		graph bindings specified in [1]. Each port node shall have a single endpoint.

		- Port 0 is the DPI input port. Its endpoint subnode shall contain a
		pclk-sample and bus-width property and a remote-endpoint property as specified
		in [1].
		- If pclk-sample is not defined, pclk-sample = 0 should be assumed for
		backward compatibility.
		- If bus-width is not defined then bus-width = 24 should be assumed for
		backward compatibility.
		bus-width = 24: 24 data lines are connected and single-edge mode
		bus-width = 12: 12 data lines are connected and dual-edge mode

		- Port 1 is the DVI output port. Its endpoint subnode shall contain a
		remote-endpoint property is specified in [1].

		[1] Documentation/devicetree/bindings/media/video-interfaces.txt


		Example
		-------
		@@ -22,6 +39,7 @@ Example
		tfp410: encoder@0 {
		compatible = "ti,tfp410";
		powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
		ti,deskew = <4>;

		ports {
		#address-cells = <1>;
		@@ -31,6 +49,8 @@ tfp410: encoder@0 {
		reg = <0>;

		tfp410_in: endpoint@0 {
		pclk-sample = <1>;
		bus-width = <24>;
		remote-endpoint = <&dpi_out>;
		};
		};

Documentation/devicetree/bindings/display/msm/gmu.txt

+8 −2

Original line number	Diff line number	Diff line
		@@ -24,7 +24,10 @@ Required properties:
		* "cxo"
		* "axi"
		* "mnoc"
		- power-domains: should be <&clock_gpucc GPU_CX_GDSC>
		- power-domains: should be:
		<&clock_gpucc GPU_CX_GDSC>
		<&clock_gpucc GPU_GX_GDSC>
		- power-domain-names: Matching names for the power domains
		- iommus: phandle to the adreno iommu
		- operating-points-v2: phandle to the OPP operating points

		@@ -51,7 +54,10 @@ Example:
		<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
		clock-names = "gmu", "cxo", "axi", "memnoc";

		power-domains = <&gpucc GPU_CX_GDSC>;
		power-domains = <&gpucc GPU_CX_GDSC>,
		<&gpucc GPU_GX_GDSC>;
		power-domain-names = "cx", "gx";

		iommus = <&adreno_smmu 5>;

		operating-points-v2 = <&gmu_opp_table>;

Documentation/devicetree/bindings/display/msm/gpu.txt

+11 −0

Original line number	Diff line number	Diff line
		@@ -22,9 +22,14 @@ Required properties:
		- qcom,adreno-630.2
		- iommus: optional phandle to an adreno iommu instance
		- operating-points-v2: optional phandle to the OPP operating points
		- interconnects: optional phandle to an interconnect provider. See
		../interconnect/interconnect.txt for details.
		- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
		control the power for the GPU. Applicable targets:
		- qcom,adreno-630.2
		- zap-shader: For a5xx and a6xx devices this node contains a memory-region that
		points to reserved memory to store the zap shader that can be used to help
		bring the GPU out of secure mode.

		Example 3xx/4xx/a5xx:

		@@ -70,6 +75,12 @@ Example a6xx (with GMU):

		operating-points-v2 = <&gpu_opp_table>;

		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;

		qcom,gmu = <&gmu>;

		zap-shader {
		memory-region = <&zap_shader_region>;
		};
		};
		};

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