Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm (a2b49102) · Commits · 戴 / test

arch/arm/Kconfig

+14 −0

Original line number	Diff line number	Diff line
		@@ -1283,6 +1283,20 @@ config ARM_ERRATA_364296
		processor into full low interrupt latency mode. ARM11MPCore
		is not affected.

		config ARM_ERRATA_764369
		bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
		depends on CPU_V7 && SMP
		help
		This option enables the workaround for erratum 764369
		affecting Cortex-A9 MPCore with two or more processors (all
		current revisions). Under certain timing circumstances, a data
		cache line maintenance operation by MVA targeting an Inner
		Shareable memory region may fail to proceed up to either the
		Point of Coherency or to the Point of Unification of the
		system. This workaround adds a DSB instruction before the
		relevant cache maintenance functions and sets a specific bit
		in the diagnostic control register of the SCU.

		endmenu

		source "arch/arm/common/Kconfig"

arch/arm/include/asm/futex.h

+17 −17

Original line number	Diff line number	Diff line
		@@ -25,17 +25,17 @@

		#ifdef CONFIG_SMP

		#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
		#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
		smp_mb(); \
		__asm__ __volatile__( \
		"1: ldrex %1, [%2]\n" \
		"1: ldrex %1, [%3]\n" \
		" " insn "\n" \
		"2: strex %1, %0, [%2]\n" \
		" teq %1, #0\n" \
		"2: strex %2, %0, [%3]\n" \
		" teq %2, #0\n" \
		" bne 1b\n" \
		" mov %0, #0\n" \
		__futex_atomic_ex_table("%4") \
		: "=&r" (ret), "=&r" (oldval) \
		__futex_atomic_ex_table("%5") \
		: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
		: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
		: "cc", "memory")

		@@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 uval, u32 __user uaddr,
		#include <linux/preempt.h>
		#include <asm/domain.h>

		#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
		#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
		__asm__ __volatile__( \
		"1: " T(ldr) " %1, [%2]\n" \
		"1: " T(ldr) " %1, [%3]\n" \
		" " insn "\n" \
		"2: " T(str) " %0, [%2]\n" \
		"2: " T(str) " %0, [%3]\n" \
		" mov %0, #0\n" \
		__futex_atomic_ex_table("%4") \
		: "=&r" (ret), "=&r" (oldval) \
		__futex_atomic_ex_table("%5") \
		: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
		: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
		: "cc", "memory")

		@@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
		int cmp = (encoded_op >> 24) & 15;
		int oparg = (encoded_op << 8) >> 20;
		int cmparg = (encoded_op << 20) >> 20;
		int oldval = 0, ret;
		int oldval = 0, ret, tmp;

		if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
		oparg = 1 << oparg;
		@@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)

		switch (op) {
		case FUTEX_OP_SET:
		__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
		__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
		break;
		case FUTEX_OP_ADD:
		__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
		__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
		break;
		case FUTEX_OP_OR:
		__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
		__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
		break;
		case FUTEX_OP_ANDN:
		__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
		__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
		break;
		case FUTEX_OP_XOR:
		__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
		__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
		break;
		default:
		ret = -ENOSYS;

arch/arm/include/asm/unistd.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -478,8 +478,8 @@
		/*
		* Unimplemented (or alternatively implemented) syscalls
		*/
		#define __IGNORE_fadvise64_64 1
		#define __IGNORE_migrate_pages 1
		#define __IGNORE_fadvise64_64
		#define __IGNORE_migrate_pages

		#endif /* __KERNEL__ */
		#endif /* __ASM_ARM_UNISTD_H */

arch/arm/kernel/smp_scu.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,7 @@

		#include <asm/smp_scu.h>
		#include <asm/cacheflush.h>
		#include <asm/cputype.h>

		#define SCU_CTRL 0x00
		#define SCU_CONFIG 0x04
		@@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
		{
		u32 scu_ctrl;

		#ifdef CONFIG_ARM_ERRATA_764369
		/* Cortex-A9 only */
		if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
		scu_ctrl = __raw_readl(scu_base + 0x30);
		if (!(scu_ctrl & 1))
		__raw_writel(scu_ctrl \| 0x1, scu_base + 0x30);
		}
		#endif

		scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
		/* already enabled? */
		if (scu_ctrl & 1)

arch/arm/kernel/vmlinux.lds.S

+12 −3

Original line number	Diff line number	Diff line
		@@ -23,8 +23,10 @@

		#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
		#define ARM_EXIT_KEEP(x) x
		#define ARM_EXIT_DISCARD(x)
		#else
		#define ARM_EXIT_KEEP(x)
		#define ARM_EXIT_DISCARD(x) x
		#endif

		OUTPUT_ARCH(arm)
		@@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
		SECTIONS
		{
		/*
		* XXX: The linker does not define how output sections are
		* assigned to input sections when there are multiple statements
		* matching the same input section name. There is no documented
		* order of matching.
		*
		* unwind exit sections must be discarded before the rest of the
		* unwind sections get included.
		*/
		@@ -47,6 +54,9 @@ SECTIONS
		*(.ARM.extab.exit.text)
		ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
		ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
		ARM_EXIT_DISCARD(EXIT_TEXT)
		ARM_EXIT_DISCARD(EXIT_DATA)
		EXIT_CALL
		#ifndef CONFIG_HOTPLUG
		*(.ARM.exidx.devexit.text)
		*(.ARM.extab.devexit.text)
		@@ -58,6 +68,8 @@ SECTIONS
		#ifndef CONFIG_SMP_ON_UP
		*(.alt.smp.init)
		#endif
		*(.discard)
		(.discard.)
		}

		#ifdef CONFIG_XIP_KERNEL
		@@ -279,9 +291,6 @@ SECTIONS

		STABS_DEBUG
		.comment 0 : { *(.comment) }

		/* Default discards */
		DISCARDS
		}

		/*

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