Commit a2aea699 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

MIPS: Move r4k FP code from r4k_switch.S to r4k_fpu.S 



Move _save_fp(), _restore_fp(), _save_msa(), _restore_msa(),
_init_msa_upper() & _init_fpu() out of r4k_switch.S & into r4k_fpu.S.
This allows us to clean up the way in which Octeon includes the default
r4k implementations of these FP functions despite replacing resume(),
and makes CONFIG_R4K_FPU more straightforwardly represent all
configurations that have an R4K-style FPU, including Octeon.

Besides cleaning up this will be useful for later patches which disable
FP support.

[ralf@linux-mips.org: Fixed build issues reported by Arnd Bergmann
<arnd@arndb.de>]

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16237/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3b2db173

arch/mips/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -2241,7 +2241,7 @@ config CPU_GENERIC_DUMP_TLB 


config CPU_R4K_FPU

	bool

	default y if !(CPU_R3000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)

	default y if !(CPU_R3000 || CPU_TX39XX)



config CPU_R4K_CACHE_TLB

	bool

arch/mips/kernel/Makefile

+9 −4
Original line number Diff line number Diff line
@@ -35,10 +35,15 @@ obj-$(CONFIG_MODULES) += module.o 
obj-$(CONFIG_FTRACE_SYSCALLS)	+= ftrace.o

obj-$(CONFIG_FUNCTION_TRACER)	+= mcount.o ftrace.o



obj-$(CONFIG_CPU_R4K_FPU)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_R3000)		+= r2300_fpu.o r2300_switch.o

obj-$(CONFIG_CPU_TX39XX)	+= r2300_fpu.o r2300_switch.o

obj-$(CONFIG_CPU_CAVIUM_OCTEON)	+= r4k_fpu.o octeon_switch.o

sw-y				:= r4k_switch.o

sw-$(CONFIG_CPU_R3000)		:= r2300_switch.o

sw-$(CONFIG_CPU_TX39XX)		:= r2300_switch.o

sw-$(CONFIG_CPU_CAVIUM_OCTEON)	:= octeon_switch.o

obj-y				+= $(sw-y)



obj-$(CONFIG_CPU_R4K_FPU)	+= r4k_fpu.o

obj-$(CONFIG_CPU_R3000)		+= r2300_fpu.o

obj-$(CONFIG_CPU_TX39XX)	+= r2300_fpu.o



obj-$(CONFIG_SMP)		+= smp.o

obj-$(CONFIG_SMP_UP)		+= smp-up.o

arch/mips/kernel/octeon_switch.S

+6 −5
Original line number Diff line number Diff line
@@ -10,12 +10,13 @@ 
 * Copyright (C) 2000 MIPS Technologies, Inc.

 *    written by Carsten Langgaard, carstenl@mips.com

 */

#include <asm/asm.h>

#include <asm/export.h>

#include <asm/asm-offsets.h>

#include <asm/mipsregs.h>

#include <asm/regdef.h>

#include <asm/stackframe.h>



#define USE_ALTERNATE_RESUME_IMPL 1

	.set push

	.set arch=mips64r2

#include "r4k_switch.S"

	.set pop

/*

 * task_struct *resume(task_struct *prev, task_struct *next,

 *		       struct thread_info *next_ti)

arch/mips/kernel/r4k_fpu.S

+196 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <asm/asm.h>

#include <asm/asmmacro.h>

#include <asm/errno.h>

#include <asm/export.h>

#include <asm/fpregdef.h>

#include <asm/mipsregs.h>

#include <asm/asm-offsets.h>
@@ -34,6 +35,201 @@ 
	.previous

	.endm



/*

 * Save a thread's fp context.

 */

LEAF(_save_fp)

EXPORT_SYMBOL(_save_fp)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \

		defined(CONFIG_CPU_MIPS32_R6)

	mfc0	t0, CP0_STATUS

#endif

	fpu_save_double a0 t0 t1		# clobbers t1

	jr	ra

	END(_save_fp)



/*

 * Restore a thread's fp context.

 */

LEAF(_restore_fp)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \

		defined(CONFIG_CPU_MIPS32_R6)

	mfc0	t0, CP0_STATUS

#endif

	fpu_restore_double a0 t0 t1		# clobbers t1

	jr	ra

	END(_restore_fp)



#ifdef CONFIG_CPU_HAS_MSA



/*

 * Save a thread's MSA vector context.

 */

LEAF(_save_msa)

EXPORT_SYMBOL(_save_msa)

	msa_save_all	a0

	jr	ra

	END(_save_msa)



/*

 * Restore a thread's MSA vector context.

 */

LEAF(_restore_msa)

	msa_restore_all	a0

	jr	ra

	END(_restore_msa)



LEAF(_init_msa_upper)

	msa_init_all_upper

	jr	ra

	END(_init_msa_upper)



#endif



/*

 * Load the FPU with signalling NANS.  This bit pattern we're using has

 * the property that no matter whether considered as single or as double

 * precision represents signaling NANS.

 *

 * The value to initialize fcr31 to comes in $a0.

 */



	.set push

	SET_HARDFLOAT



LEAF(_init_fpu)

	mfc0	t0, CP0_STATUS

	li	t1, ST0_CU1

	or	t0, t1

	mtc0	t0, CP0_STATUS

	enable_fpu_hazard



	ctc1	a0, fcr31



	li	t1, -1				# SNaN



#ifdef CONFIG_64BIT

	sll	t0, t0, 5

	bgez	t0, 1f				# 16 / 32 register mode?



	dmtc1	t1, $f1

	dmtc1	t1, $f3

	dmtc1	t1, $f5

	dmtc1	t1, $f7

	dmtc1	t1, $f9

	dmtc1	t1, $f11

	dmtc1	t1, $f13

	dmtc1	t1, $f15

	dmtc1	t1, $f17

	dmtc1	t1, $f19

	dmtc1	t1, $f21

	dmtc1	t1, $f23

	dmtc1	t1, $f25

	dmtc1	t1, $f27

	dmtc1	t1, $f29

	dmtc1	t1, $f31

1:

#endif



#ifdef CONFIG_CPU_MIPS32

	mtc1	t1, $f0

	mtc1	t1, $f1

	mtc1	t1, $f2

	mtc1	t1, $f3

	mtc1	t1, $f4

	mtc1	t1, $f5

	mtc1	t1, $f6

	mtc1	t1, $f7

	mtc1	t1, $f8

	mtc1	t1, $f9

	mtc1	t1, $f10

	mtc1	t1, $f11

	mtc1	t1, $f12

	mtc1	t1, $f13

	mtc1	t1, $f14

	mtc1	t1, $f15

	mtc1	t1, $f16

	mtc1	t1, $f17

	mtc1	t1, $f18

	mtc1	t1, $f19

	mtc1	t1, $f20

	mtc1	t1, $f21

	mtc1	t1, $f22

	mtc1	t1, $f23

	mtc1	t1, $f24

	mtc1	t1, $f25

	mtc1	t1, $f26

	mtc1	t1, $f27

	mtc1	t1, $f28

	mtc1	t1, $f29

	mtc1	t1, $f30

	mtc1	t1, $f31



#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)

	.set    push

	.set    MIPS_ISA_LEVEL_RAW

	.set	fp=64

	sll     t0, t0, 5			# is Status.FR set?

	bgez    t0, 1f				# no: skip setting upper 32b



	mthc1   t1, $f0

	mthc1   t1, $f1

	mthc1   t1, $f2

	mthc1   t1, $f3

	mthc1   t1, $f4

	mthc1   t1, $f5

	mthc1   t1, $f6

	mthc1   t1, $f7

	mthc1   t1, $f8

	mthc1   t1, $f9

	mthc1   t1, $f10

	mthc1   t1, $f11

	mthc1   t1, $f12

	mthc1   t1, $f13

	mthc1   t1, $f14

	mthc1   t1, $f15

	mthc1   t1, $f16

	mthc1   t1, $f17

	mthc1   t1, $f18

	mthc1   t1, $f19

	mthc1   t1, $f20

	mthc1   t1, $f21

	mthc1   t1, $f22

	mthc1   t1, $f23

	mthc1   t1, $f24

	mthc1   t1, $f25

	mthc1   t1, $f26

	mthc1   t1, $f27

	mthc1   t1, $f28

	mthc1   t1, $f29

	mthc1   t1, $f30

	mthc1   t1, $f31

1:	.set    pop

#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */

#else

	.set	MIPS_ISA_ARCH_LEVEL_RAW

	dmtc1	t1, $f0

	dmtc1	t1, $f2

	dmtc1	t1, $f4

	dmtc1	t1, $f6

	dmtc1	t1, $f8

	dmtc1	t1, $f10

	dmtc1	t1, $f12

	dmtc1	t1, $f14

	dmtc1	t1, $f16

	dmtc1	t1, $f18

	dmtc1	t1, $f20

	dmtc1	t1, $f22

	dmtc1	t1, $f24

	dmtc1	t1, $f26

	dmtc1	t1, $f28

	dmtc1	t1, $f30

#endif

	jr	ra

	END(_init_fpu)



	.set pop	/* SET_HARDFLOAT */



	.set	noreorder



/**

arch/mips/kernel/r4k_switch.S

+0 −203
Original line number Diff line number Diff line
@@ -12,8 +12,6 @@ 
 */

#include <asm/asm.h>

#include <asm/cachectl.h>

#include <asm/export.h>

#include <asm/fpregdef.h>

#include <asm/mipsregs.h>

#include <asm/asm-offsets.h>

#include <asm/regdef.h>
@@ -22,10 +20,6 @@ 


#include <asm/asmmacro.h>



/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */

#undef fp



#ifndef USE_ALTERNATE_RESUME_IMPL

/*

 * task_struct *resume(task_struct *prev, task_struct *next,

 *		       struct thread_info *next_ti)
@@ -63,200 +57,3 @@ 
	move	v0, a0

	jr	ra

	END(resume)
 


#endif /* USE_ALTERNATE_RESUME_IMPL */



/*

 * Save a thread's fp context.

 */

LEAF(_save_fp)

EXPORT_SYMBOL(_save_fp)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \

		defined(CONFIG_CPU_MIPS32_R6)

	mfc0	t0, CP0_STATUS

#endif

	fpu_save_double a0 t0 t1		# clobbers t1

	jr	ra

	END(_save_fp)



/*

 * Restore a thread's fp context.

 */

LEAF(_restore_fp)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \

		defined(CONFIG_CPU_MIPS32_R6)

	mfc0	t0, CP0_STATUS

#endif

	fpu_restore_double a0 t0 t1		# clobbers t1

	jr	ra

	END(_restore_fp)



#ifdef CONFIG_CPU_HAS_MSA



/*

 * Save a thread's MSA vector context.

 */

LEAF(_save_msa)

EXPORT_SYMBOL(_save_msa)

	msa_save_all	a0

	jr	ra

	END(_save_msa)



/*

 * Restore a thread's MSA vector context.

 */

LEAF(_restore_msa)

	msa_restore_all	a0

	jr	ra

	END(_restore_msa)



LEAF(_init_msa_upper)

	msa_init_all_upper

	jr	ra

	END(_init_msa_upper)



#endif



/*

 * Load the FPU with signalling NANS.  This bit pattern we're using has

 * the property that no matter whether considered as single or as double

 * precision represents signaling NANS.

 *

 * The value to initialize fcr31 to comes in $a0.

 */



	.set push

	SET_HARDFLOAT



LEAF(_init_fpu)

	mfc0	t0, CP0_STATUS

	li	t1, ST0_CU1

	or	t0, t1

	mtc0	t0, CP0_STATUS

	enable_fpu_hazard



	ctc1	a0, fcr31



	li	t1, -1				# SNaN



#ifdef CONFIG_64BIT

	sll	t0, t0, 5

	bgez	t0, 1f				# 16 / 32 register mode?



	dmtc1	t1, $f1

	dmtc1	t1, $f3

	dmtc1	t1, $f5

	dmtc1	t1, $f7

	dmtc1	t1, $f9

	dmtc1	t1, $f11

	dmtc1	t1, $f13

	dmtc1	t1, $f15

	dmtc1	t1, $f17

	dmtc1	t1, $f19

	dmtc1	t1, $f21

	dmtc1	t1, $f23

	dmtc1	t1, $f25

	dmtc1	t1, $f27

	dmtc1	t1, $f29

	dmtc1	t1, $f31

1:

#endif



#ifdef CONFIG_CPU_MIPS32

	mtc1	t1, $f0

	mtc1	t1, $f1

	mtc1	t1, $f2

	mtc1	t1, $f3

	mtc1	t1, $f4

	mtc1	t1, $f5

	mtc1	t1, $f6

	mtc1	t1, $f7

	mtc1	t1, $f8

	mtc1	t1, $f9

	mtc1	t1, $f10

	mtc1	t1, $f11

	mtc1	t1, $f12

	mtc1	t1, $f13

	mtc1	t1, $f14

	mtc1	t1, $f15

	mtc1	t1, $f16

	mtc1	t1, $f17

	mtc1	t1, $f18

	mtc1	t1, $f19

	mtc1	t1, $f20

	mtc1	t1, $f21

	mtc1	t1, $f22

	mtc1	t1, $f23

	mtc1	t1, $f24

	mtc1	t1, $f25

	mtc1	t1, $f26

	mtc1	t1, $f27

	mtc1	t1, $f28

	mtc1	t1, $f29

	mtc1	t1, $f30

	mtc1	t1, $f31



#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)

	.set    push

	.set    MIPS_ISA_LEVEL_RAW

	.set	fp=64

	sll     t0, t0, 5			# is Status.FR set?

	bgez    t0, 1f				# no: skip setting upper 32b



	mthc1   t1, $f0

	mthc1   t1, $f1

	mthc1   t1, $f2

	mthc1   t1, $f3

	mthc1   t1, $f4

	mthc1   t1, $f5

	mthc1   t1, $f6

	mthc1   t1, $f7

	mthc1   t1, $f8

	mthc1   t1, $f9

	mthc1   t1, $f10

	mthc1   t1, $f11

	mthc1   t1, $f12

	mthc1   t1, $f13

	mthc1   t1, $f14

	mthc1   t1, $f15

	mthc1   t1, $f16

	mthc1   t1, $f17

	mthc1   t1, $f18

	mthc1   t1, $f19

	mthc1   t1, $f20

	mthc1   t1, $f21

	mthc1   t1, $f22

	mthc1   t1, $f23

	mthc1   t1, $f24

	mthc1   t1, $f25

	mthc1   t1, $f26

	mthc1   t1, $f27

	mthc1   t1, $f28

	mthc1   t1, $f29

	mthc1   t1, $f30

	mthc1   t1, $f31

1:	.set    pop

#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */

#else

	.set	MIPS_ISA_ARCH_LEVEL_RAW

	dmtc1	t1, $f0

	dmtc1	t1, $f2

	dmtc1	t1, $f4

	dmtc1	t1, $f6

	dmtc1	t1, $f8

	dmtc1	t1, $f10

	dmtc1	t1, $f12

	dmtc1	t1, $f14

	dmtc1	t1, $f16

	dmtc1	t1, $f18

	dmtc1	t1, $f20

	dmtc1	t1, $f22

	dmtc1	t1, $f24

	dmtc1	t1, $f26

	dmtc1	t1, $f28

	dmtc1	t1, $f30

#endif

	jr	ra

	END(_init_fpu)



	.set pop	/* SET_HARDFLOAT */

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