Commit a2a3e46c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'ti-k3-dt-for-v5.8' of... 

Merge tag 'ti-k3-dt-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt

Texas Instruments K3 SoC DT updates for v5.8

- Add DSS support for both AM65x and J721e
- Add watchdog support for J721e
- Add EHRPWM support for AM65x
- Add Thermal support for AM65x

* tag 'ti-k3-dt-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
  arm64: dts: ti: k3-j721e-main: Add main domain watchdog entries
  arm64: dts: ti: k3-am65-main: Add ehrpwm nodes
  arm64: dts: ti: am654: Add thermal zones
  arm64: dts: ti: am65-wakeup: Add VTM node
  arm64: dts: ti: k3-j721e-common-proc-board: add assigned clks for DSS
  arm64: dts: ti: k3-j721e-main: Add DSS node
  arm64: dts: ti: am654: Add DSS node

Link: https://lore.kernel.org/r/7484d3c9-323f-36a3-f0df-1287586f356d@ti.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 863c0b59 cae80943

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

+104 −0
Original line number Diff line number Diff line
@@ -287,6 +287,17 @@ 
			mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */

					<0x4090 0x3>; /* SERDES1 lane select */

		};



		dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {

			compatible = "syscon";

			reg = <0x0000041E0 0x14>;

		};



		ehrpwm_tbclk: syscon@4140 {

			compatible = "ti,am654-ehrpwm-tbclk", "syscon";

			reg = <0x4140 0x18>;

			#clock-cells = <1>;

		};

	};



	dwc3_0: dwc3@4000000 {
@@ -746,4 +757,97 @@ 
			};

		};

	};



	dss: dss@04a00000 {

		compatible = "ti,am65x-dss";

		reg =	<0x0 0x04a00000 0x0 0x1000>, /* common */

			<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */

			<0x0 0x04a06000 0x0 0x1000>, /* vid */

			<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */

			<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */

			<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */

			<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */

		reg-names = "common", "vidl1", "vid",

			"ovr1", "ovr2", "vp1", "vp2";



		ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;



		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;



		clocks =	<&k3_clks 67 1>,

				<&k3_clks 216 1>,

				<&k3_clks 67 2>;

		clock-names = "fck", "vp1", "vp2";



		/*

		 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via

		 * DIV1. See "Figure 12-3365. DSS Integration"

		 * in AM65x TRM for details.

		 */

		assigned-clocks = <&k3_clks 67 2>;

		assigned-clock-parents = <&k3_clks 67 5>;



		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;



		status = "disabled";



		dss_ports: ports {

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	ehrpwm0: pwm@3000000 {

		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";

		#pwm-cells = <3>;

		reg = <0x0 0x3000000 0x0 0x100>;

		power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;

		clock-names = "tbclk", "fck";

	};



	ehrpwm1: pwm@3010000 {

		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";

		#pwm-cells = <3>;

		reg = <0x0 0x3010000 0x0 0x100>;

		power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;

		clock-names = "tbclk", "fck";

	};



	ehrpwm2: pwm@3020000 {

		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";

		#pwm-cells = <3>;

		reg = <0x0 0x3020000 0x0 0x100>;

		power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;

		clock-names = "tbclk", "fck";

	};



	ehrpwm3: pwm@3030000 {

		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";

		#pwm-cells = <3>;

		reg = <0x0 0x3030000 0x0 0x100>;

		power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;

		clock-names = "tbclk", "fck";

	};



	ehrpwm4: pwm@3040000 {

		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";

		#pwm-cells = <3>;

		reg = <0x0 0x3040000 0x0 0x100>;

		power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;

		clock-names = "tbclk", "fck";

	};



	ehrpwm5: pwm@3050000 {

		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";

		#pwm-cells = <3>;

		reg = <0x0 0x3050000 0x0 0x100>;

		power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;

		clock-names = "tbclk", "fck";

	};

};

arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -89,4 +89,15 @@ 
		clocks = <&k3_clks 59 0>;

		clock-names = "gpio";

	};



	wkup_vtm0: thermal@42050000 {

		compatible = "ti,am654-vtm";

		reg = <0x42050000 0x25c>;

		power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;

		#thermal-sensor-cells = <1>;

	};



	thermal_zones: thermal-zones {

		#include "k3-am654-industrial-thermal.dtsi"

	};

};

arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi

0 → 100644
+45 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0



#include <dt-bindings/thermal/thermal.h>



mpu0_thermal: mpu0_thermal {

	polling-delay-passive = <250>; /* milliseconds */

	polling-delay = <500>; /* milliseconds */

	thermal-sensors = <&wkup_vtm0 0>;



	trips {

		mpu0_crit: mpu0_crit {

			temperature = <125000>; /* milliCelsius */

			hysteresis = <2000>; /* milliCelsius */

			type = "critical";

		};

	};

};



mpu1_thermal: mpu1_thermal {

	polling-delay-passive = <250>; /* milliseconds */

	polling-delay = <500>; /* milliseconds */

	thermal-sensors = <&wkup_vtm0 1>;



	trips {

		mpu1_crit: mpu1_crit {

			temperature = <125000>; /* milliCelsius */

			hysteresis = <2000>; /* milliCelsius */

			type = "critical";

		};

	};

};



mcu_thermal: mcu_thermal {

	polling-delay-passive = <250>; /* milliseconds */

	polling-delay = <500>; /* milliseconds */

	thermal-sensors = <&wkup_vtm0 2>;



	trips {

		mcu_crit: mcu_crit {

			temperature = <125000>; /* milliCelsius */

			hysteresis = <2000>; /* milliCelsius */

			type = "critical";

		};

	};

};

arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts

+20 −0
Original line number Diff line number Diff line
@@ -472,3 +472,23 @@ 
	phy-mode = "rgmii-rxid";

	phy-handle = <&phy0>;

};



&dss {

	/*

	 * These clock assignments are chosen to enable the following outputs:

	 *

	 * VP0 - DisplayPort SST

	 * VP1 - DPI0

	 * VP2 - DSI

	 * VP3 - DPI1

	 */



	assigned-clocks = <&k3_clks 152 1>,

			  <&k3_clks 152 4>,

			  <&k3_clks 152 9>,

			  <&k3_clks 152 13>;

	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */

				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */

				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */

				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */

};

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+75 −0
Original line number Diff line number Diff line
@@ -736,6 +736,63 @@ 
		};

	};



	dss: dss@04a00000 {

		compatible = "ti,j721e-dss";

		reg =

			<0x00 0x04a00000 0x00 0x10000>, /* common_m */

			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/

			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/

			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/



			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */

			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */

			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */

			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */



			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */

			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */

			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */

			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */



			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */

			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */

			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */

			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */

			<0x00 0x04af0000 0x00 0x10000>; /* wb */



		reg-names = "common_m", "common_s0",

			"common_s1", "common_s2",

			"vidl1", "vidl2","vid1","vid2",

			"ovr1", "ovr2", "ovr3", "ovr4",

			"vp1", "vp2", "vp3", "vp4",

			"wb";



		clocks =	<&k3_clks 152 0>,

				<&k3_clks 152 1>,

				<&k3_clks 152 4>,

				<&k3_clks 152 9>,

				<&k3_clks 152 13>;

		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";



		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;



		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "common_m",

				  "common_s0",

				  "common_s1",

				  "common_s2";



		status = "disabled";



		dss_ports: ports {

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	mcasp0: mcasp@2b00000 {

		compatible = "ti,am33xx-mcasp-audio";

		reg = <0x0 0x02b00000 0x0 0x2000>,
@@ -963,4 +1020,22 @@ 


		status = "disabled";

	};



	watchdog0: watchdog@2200000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x0 0x2200000 0x0 0x100>;

		clocks = <&k3_clks 252 1>;

		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 252 1>;

		assigned-clock-parents = <&k3_clks 252 5>;

	};



	watchdog1: watchdog@2210000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x0 0x2210000 0x0 0x100>;

		clocks = <&k3_clks 253 1>;

		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 253 1>;

		assigned-clock-parents = <&k3_clks 253 5>;

	};

};

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