Commit a2956ecd authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'qed-janitorial' 



Yuval Mintz says:

====================
qed*: Janitorial series [semantic & prints]

Some day 1 slips in coding style exist in the qed* code
[incorrect alignments, conditions using (== 0), etc.].
This series comes to address those, and do some additional
cosmetic changes along the way [such as reducing the number of lines
for function declerations].

The series is broken to 3 parts - purely semantic changes, cosmetic
changes that required minor changes in the code, and print-related
changes. All-in-all, no real change in driver behavior is expected.

[This is a repost; Original was sent when net-next closed].

Please consider applying this to `net-next'.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 54be3d98 525ef5c0

drivers/net/ethernet/qlogic/qed/qed_cxt.c

+18 −29
Original line number Diff line number Diff line
@@ -378,8 +378,7 @@ static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn, 
}



u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,

				enum protocol_type	type,

				u32			*vf_cid)

				enum protocol_type type, u32 *vf_cid)

{

	if (vf_cid)

		*vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
@@ -405,10 +404,10 @@ u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn, 
	return cnt;

}



static void

qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,

static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,

					enum protocol_type proto,

			    u8 seg, u8 seg_type, u32 count, bool has_fl)

					u8 seg,

					u8 seg_type, u32 count, bool has_fl)

{

	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
@@ -420,8 +419,7 @@ qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn, 


static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,

				 struct qed_ilt_cli_blk *p_blk,

				 u32 start_line, u32 total_size,

				 u32 elem_size)

				 u32 start_line, u32 total_size, u32 elem_size)

{

	u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
@@ -448,8 +446,7 @@ static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn, 
		p_cli->first.val = *p_line;



	p_cli->active = true;

	*p_line += DIV_ROUND_UP(p_blk->total_size,

				p_blk->real_size_in_page);

	*p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);

	p_cli->last.val = *p_line - 1;



	DP_VERBOSE(p_hwfn, QED_MSG_ILT,
@@ -926,12 +923,9 @@ static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn, 
		void *p_virt;

		u32 size;



		size = min_t(u32, sz_left,

			     p_blk->real_size_in_page);

		size = min_t(u32, sz_left, p_blk->real_size_in_page);

		p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,

					    size,

					    &p_phys,

					    GFP_KERNEL);

					    size, &p_phys, GFP_KERNEL);

		if (!p_virt)

			return -ENOMEM;

		memset(p_virt, 0, size);
@@ -976,7 +970,7 @@ static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 
		for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {

			p_blk = &clients[i].pf_blks[j];

			rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);

			if (rc != 0)

			if (rc)

				goto ilt_shadow_fail;

		}

		for (k = 0; k < p_mngr->vf_count; k++) {
@@ -985,7 +979,7 @@ static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 


				p_blk = &clients[i].vf_blks[j];

				rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);

				if (rc != 0)

				if (rc)

					goto ilt_shadow_fail;

			}

		}
@@ -1672,7 +1666,7 @@ static void qed_tm_init_pf(struct qed_hwfn *p_hwfn) 
		     p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);



		STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);

		active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);

		active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0);



		tm_offset += tm_iids.pf_tids[i];

	}
@@ -1702,8 +1696,7 @@ void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn) 
}



int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,

			enum protocol_type type,

			u32 *p_cid)

			enum protocol_type type, u32 *p_cid)

{

	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	u32 rel_cid;
@@ -1717,8 +1710,7 @@ int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 
				      p_mngr->acquired[type].max_count);



	if (rel_cid >= p_mngr->acquired[type].max_count) {

		DP_NOTICE(p_hwfn, "no CID available for protocol %d\n",

			  type);

		DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type);

		return -EINVAL;

	}
@@ -1730,8 +1722,7 @@ int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 
}



static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn,

				      u32 cid,

				      enum protocol_type *p_type)

				      u32 cid, enum protocol_type *p_type)

{

	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	struct qed_cid_acquired_map *p_map;
@@ -1763,8 +1754,7 @@ static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn, 
	return true;

}



void qed_cxt_release_cid(struct qed_hwfn *p_hwfn,

			 u32 cid)

void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid)

{

	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	enum protocol_type type;
@@ -1781,8 +1771,7 @@ void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, 
	__clear_bit(rel_cid, p_mngr->acquired[type].cid_map);

}



int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn,

			 struct qed_cxt_info *p_info)

int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info)

{

	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	u32 conn_cxt_size, hw_p_size, cxts_per_p, line;

drivers/net/ethernet/qlogic/qed/qed_dev.c

+49 −66
Original line number Diff line number Diff line
@@ -43,8 +43,7 @@ enum BAR_ID { 
	BAR_ID_1        /* Used for doorbells */

};



static u32 qed_hw_bar_size(struct qed_hwfn	*p_hwfn,

			   enum BAR_ID		bar_id)

static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)

{

	u32 bar_reg = (bar_id == BAR_ID_0 ?

		       PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
@@ -69,8 +68,7 @@ static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 
	}

}



void qed_init_dp(struct qed_dev *cdev,

		 u32 dp_module, u8 dp_level)

void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)

{

	u32 i;
@@ -542,8 +540,7 @@ int qed_resc_alloc(struct qed_dev *cdev) 
	cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);

	if (!cdev->reset_stats) {

		DP_NOTICE(cdev, "Failed to allocate reset statistics\n");

		rc = -ENOMEM;

		goto alloc_err;

		goto alloc_no_mem;

	}



	return 0;
@@ -604,8 +601,7 @@ int qed_final_cleanup(struct qed_hwfn *p_hwfn, 


	/* Make sure notification is not set before initiating final cleanup */

	if (REG_RD(p_hwfn, addr)) {

		DP_NOTICE(

			p_hwfn,

		DP_NOTICE(p_hwfn,

			  "Unexpected; Found final cleanup notification before initiating final cleanup\n");

		REG_WR(p_hwfn, addr, 0);

	}
@@ -700,17 +696,14 @@ static void qed_init_cau_rt_data(struct qed_dev *cdev) 
				continue;



			qed_init_cau_sb_entry(p_hwfn, &sb_entry,

					      p_block->function_id,

					      0, 0);

			STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2,

					 sb_entry);

					      p_block->function_id, 0, 0);

			STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);

		}

	}

}



static int qed_hw_init_common(struct qed_hwfn *p_hwfn,

			      struct qed_ptt *p_ptt,

			      int hw_mode)

			      struct qed_ptt *p_ptt, int hw_mode)

{

	struct qed_qm_info *qm_info = &p_hwfn->qm_info;

	struct qed_qm_common_rt_init_params params;
@@ -758,7 +751,7 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 
	qed_port_unpretend(p_hwfn, p_ptt);



	rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);

	if (rc != 0)

	if (rc)

		return rc;



	qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
@@ -787,13 +780,12 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 
}



static int qed_hw_init_port(struct qed_hwfn *p_hwfn,

			    struct qed_ptt *p_ptt,

			    int hw_mode)

			    struct qed_ptt *p_ptt, int hw_mode)

{

	int rc = 0;



	rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);

	if (rc != 0)

	if (rc)

		return rc;



	if (hw_mode & (1 << MODE_MF_SI)) {
@@ -847,7 +839,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 
	qed_int_igu_init_rt(p_hwfn);



	/* Set VLAN in NIG if needed */

	if (hw_mode & (1 << MODE_MF_SD)) {

	if (hw_mode & BIT(MODE_MF_SD)) {

		DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");

		STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);

		STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
@@ -855,7 +847,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 
	}



	/* Enable classification by MAC if needed */

	if (hw_mode & (1 << MODE_MF_SI)) {

	if (hw_mode & BIT(MODE_MF_SI)) {

		DP_VERBOSE(p_hwfn, NETIF_MSG_HW,

			   "Configuring TAGMAC_CLS_TYPE\n");

		STORE_RT_REG(p_hwfn,
@@ -870,7 +862,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 


	/* Cleanup chip from previous driver if such remains exist */

	rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);

	if (rc != 0)

	if (rc)

		return rc;



	/* PF Init sequence */
@@ -949,8 +941,7 @@ static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 
	/* Read shadow of current MFW mailbox */

	qed_mcp_read_mb(p_hwfn, p_main_ptt);

	memcpy(p_hwfn->mcp_info->mfw_mb_shadow,

	       p_hwfn->mcp_info->mfw_mb_cur,

	       p_hwfn->mcp_info->mfw_mb_length);

	       p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);

}



int qed_hw_init(struct qed_dev *cdev,
@@ -970,7 +961,7 @@ int qed_hw_init(struct qed_dev *cdev, 


	if (IS_PF(cdev)) {

		rc = qed_init_fw_data(cdev, bin_fw_data);

		if (rc != 0)

		if (rc)

			return rc;

	}
@@ -987,8 +978,7 @@ int qed_hw_init(struct qed_dev *cdev, 


		qed_calc_hw_mode(p_hwfn);



		rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,

				      &load_code);

		rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);

		if (rc) {

			DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");

			return rc;
@@ -1065,9 +1055,8 @@ int qed_hw_init(struct qed_dev *cdev, 
}



#define QED_HW_STOP_RETRY_LIMIT (10)

static inline void qed_hw_timers_stop(struct qed_dev *cdev,

				      struct qed_hwfn *p_hwfn,

				      struct qed_ptt *p_ptt)

static void qed_hw_timers_stop(struct qed_dev *cdev,

			       struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

{

	int i;
@@ -1078,8 +1067,7 @@ static inline void qed_hw_timers_stop(struct qed_dev *cdev, 
	for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {

		if ((!qed_rd(p_hwfn, p_ptt,

			     TM_REG_PF_SCAN_ACTIVE_CONN)) &&

		    (!qed_rd(p_hwfn, p_ptt,

			     TM_REG_PF_SCAN_ACTIVE_TASK)))

		    (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))

			break;



		/* Dependent on number of connection/tasks, possibly
@@ -1184,8 +1172,7 @@ void qed_hw_stop_fastpath(struct qed_dev *cdev) 
		}



		DP_VERBOSE(p_hwfn,

			   NETIF_MSG_IFDOWN,

			   "Shutting down the fastpath\n");

			   NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");



		qed_wr(p_hwfn, p_ptt,

		       NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
@@ -1213,14 +1200,13 @@ void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 
	       NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);

}



static int qed_reg_assert(struct qed_hwfn *hwfn,

			  struct qed_ptt *ptt, u32 reg,

			  bool expected)

static int qed_reg_assert(struct qed_hwfn *p_hwfn,

			  struct qed_ptt *p_ptt, u32 reg, bool expected)

{

	u32 assert_val = qed_rd(hwfn, ptt, reg);

	u32 assert_val = qed_rd(p_hwfn, p_ptt, reg);



	if (assert_val != expected) {

		DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n",

		DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n",

			  reg, expected);

		return -EINVAL;

	}
@@ -1300,8 +1286,7 @@ static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 


	/* Clean Previous errors if such exist */

	qed_wr(p_hwfn, p_hwfn->p_main_ptt,

	       PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,

	       1 << p_hwfn->abs_pf_id);

	       PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);



	/* enable internal target-read */

	qed_wr(p_hwfn, p_hwfn->p_main_ptt,
@@ -1311,7 +1296,8 @@ static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 
static void get_function_id(struct qed_hwfn *p_hwfn)

{

	/* ME Register */

	p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR);

	p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,

						  PXP_PF_ME_OPAQUE_ADDR);



	p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
@@ -1320,6 +1306,10 @@ static void get_function_id(struct qed_hwfn *p_hwfn) 
				      PXP_CONCRETE_FID_PFID);

	p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,

				    PXP_CONCRETE_FID_PORT);



	DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,

		   "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",

		   p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);

}



static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
@@ -1411,8 +1401,7 @@ static int qed_hw_get_resc(struct qed_hwfn *p_hwfn) 
	return 0;

}



static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,

			       struct qed_ptt *p_ptt)

static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

{

	u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;

	u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
@@ -1466,8 +1455,7 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, 
		p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;

		break;

	default:

		DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n",

			  core_cfg);

		DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);

		break;

	}
@@ -1478,11 +1466,11 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, 
	link_temp = qed_rd(p_hwfn, p_ptt,

			   port_cfg_addr +

			   offsetof(struct nvm_cfg1_port, speed_cap_mask));

	link->speed.advertised_speeds =

		link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;

	link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;

	link->speed.advertised_speeds = link_temp;



	p_hwfn->mcp_info->link_capabilities.speed_capabilities =

						link->speed.advertised_speeds;

	link_temp = link->speed.advertised_speeds;

	p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;



	link_temp = qed_rd(p_hwfn, p_ptt,

			   port_cfg_addr +
@@ -1511,8 +1499,7 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, 
		link->speed.forced_speed = 100000;

		break;

	default:

		DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n",

			  link_temp);

		DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);

	}



	link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
@@ -1622,10 +1609,10 @@ static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 


	DP_VERBOSE(p_hwfn,

		   NETIF_MSG_PROBE,

		   "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",

		   "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",

		   p_hwfn->rel_pf_id,

		   p_hwfn->abs_pf_id,

		   p_hwfn->num_funcs_on_engine);

		   p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);

}



static int
@@ -1697,10 +1684,9 @@ static int qed_get_dev_info(struct qed_dev *cdev) 
	u32 tmp;



	/* Read Vendor Id / Device Id */

	pci_read_config_word(cdev->pdev, PCI_VENDOR_ID,

			     &cdev->vendor_id);

	pci_read_config_word(cdev->pdev, PCI_DEVICE_ID,

			     &cdev->device_id);

	pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);

	pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);



	cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,

				     MISCS_REG_CHIP_NUM);

	cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
@@ -1776,7 +1762,7 @@ static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 
	/* First hwfn learns basic information, e.g., number of hwfns */

	if (!p_hwfn->my_id) {

		rc = qed_get_dev_info(p_hwfn->cdev);

		if (rc != 0)

		if (rc)

			goto err1;

	}
@@ -2177,8 +2163,7 @@ int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 
	return 0;

}



int qed_fw_vport(struct qed_hwfn *p_hwfn,

		 u8 src_id, u8 *dst_id)

int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)

{

	if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {

		u8 min, max;
@@ -2197,8 +2182,7 @@ int qed_fw_vport(struct qed_hwfn *p_hwfn, 
	return 0;

}



int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,

		   u8 src_id, u8 *dst_id)

int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)

{

	if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {

		u8 min, max;
@@ -2380,8 +2364,7 @@ static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 
 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.

 */

static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,

			      u16 vport_id, u32 req_rate,

			      u32 min_pf_rate)

			      u16 vport_id, u32 req_rate, u32 min_pf_rate)

{

	u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;

	int non_requested_count = 0, req_count = 0, i, num_vports;
@@ -2465,7 +2448,7 @@ static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 


	rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);



	if (rc == 0)

	if (!rc)

		qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,

						 p_link->min_pf_rate);

	else

drivers/net/ethernet/qlogic/qed/qed_hw.c

+53 −84
Original line number Diff line number Diff line
@@ -44,8 +44,7 @@ struct qed_ptt_pool { 


int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn)

{

	struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool),

					      GFP_KERNEL);

	struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), GFP_KERNEL);

	int i;



	if (!p_pool)
@@ -113,16 +112,14 @@ struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn) 
	return NULL;

}



void qed_ptt_release(struct qed_hwfn *p_hwfn,

		     struct qed_ptt *p_ptt)

void qed_ptt_release(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

{

	spin_lock_bh(&p_hwfn->p_ptt_pool->lock);

	list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);

	spin_unlock_bh(&p_hwfn->p_ptt_pool->lock);

}



u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn,

			struct qed_ptt *p_ptt)

u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

{

	/* The HW is using DWORDS and we need to translate it to Bytes */

	return le32_to_cpu(p_ptt->pxp.offset) << 2;
@@ -141,8 +138,7 @@ u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt) 
}



void qed_ptt_set_win(struct qed_hwfn *p_hwfn,

		     struct qed_ptt *p_ptt,

		     u32 new_hw_addr)

		     struct qed_ptt *p_ptt, u32 new_hw_addr)

{

	u32 prev_hw_addr;
@@ -166,8 +162,7 @@ void qed_ptt_set_win(struct qed_hwfn *p_hwfn, 
}



static u32 qed_set_ptt(struct qed_hwfn *p_hwfn,

		       struct qed_ptt *p_ptt,

		       u32 hw_addr)

		       struct qed_ptt *p_ptt, u32 hw_addr)

{

	u32 win_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt);

	u32 offset;
@@ -224,10 +219,7 @@ u32 qed_rd(struct qed_hwfn *p_hwfn, 


static void qed_memcpy_hw(struct qed_hwfn *p_hwfn,

			  struct qed_ptt *p_ptt,

			  void *addr,

			  u32 hw_addr,

			  size_t n,

			  bool to_device)

			  void *addr, u32 hw_addr, size_t n, bool to_device)

{

	u32 dw_count, *host_addr, hw_offset;

	size_t quota, done = 0;
@@ -259,8 +251,7 @@ static void qed_memcpy_hw(struct qed_hwfn *p_hwfn, 
}



void qed_memcpy_from(struct qed_hwfn *p_hwfn,

		     struct qed_ptt *p_ptt,

		     void *dest, u32 hw_addr, size_t n)

		     struct qed_ptt *p_ptt, void *dest, u32 hw_addr, size_t n)

{

	DP_VERBOSE(p_hwfn, NETIF_MSG_HW,

		   "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
@@ -270,8 +261,7 @@ void qed_memcpy_from(struct qed_hwfn *p_hwfn, 
}



void qed_memcpy_to(struct qed_hwfn *p_hwfn,

		   struct qed_ptt *p_ptt,

		   u32 hw_addr, void *src, size_t n)

		   struct qed_ptt *p_ptt, u32 hw_addr, void *src, size_t n)

{

	DP_VERBOSE(p_hwfn, NETIF_MSG_HW,

		   "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
@@ -280,9 +270,7 @@ void qed_memcpy_to(struct qed_hwfn *p_hwfn, 
	qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);

}



void qed_fid_pretend(struct qed_hwfn *p_hwfn,

		     struct qed_ptt *p_ptt,

		     u16 fid)

void qed_fid_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 fid)

{

	u16 control = 0;
@@ -309,8 +297,7 @@ void qed_fid_pretend(struct qed_hwfn *p_hwfn, 
}



void qed_port_pretend(struct qed_hwfn *p_hwfn,

		      struct qed_ptt *p_ptt,

		      u8 port_id)

		      struct qed_ptt *p_ptt, u8 port_id)

{

	u16 control = 0;
@@ -326,8 +313,7 @@ void qed_port_pretend(struct qed_hwfn *p_hwfn, 
	       *(u32 *)&p_ptt->pxp.pretend);

}



void qed_port_unpretend(struct qed_hwfn *p_hwfn,

			struct qed_ptt *p_ptt)

void qed_port_unpretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

{

	u16 control = 0;
@@ -429,28 +415,27 @@ u32 qed_dmae_idx_to_go_cmd(u8 idx) 
	return DMAE_REG_GO_C0 + (idx << 2);

}



static int

qed_dmae_post_command(struct qed_hwfn *p_hwfn,

static int qed_dmae_post_command(struct qed_hwfn *p_hwfn,

				 struct qed_ptt *p_ptt)

{

	struct dmae_cmd *command = p_hwfn->dmae_info.p_dmae_cmd;

	struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;

	u8 idx_cmd = p_hwfn->dmae_info.channel, i;

	int qed_status = 0;



	/* verify address is not NULL */

	if ((((command->dst_addr_lo == 0) && (command->dst_addr_hi == 0)) ||

	     ((command->src_addr_lo == 0) && (command->src_addr_hi == 0)))) {

	if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||

	     ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {

		DP_NOTICE(p_hwfn,

			  "source or destination address 0 idx_cmd=%d\n"

			  "opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n",

			  idx_cmd,

			   le32_to_cpu(command->opcode),

			   le16_to_cpu(command->opcode_b),

			   le16_to_cpu(command->length_dw),

			   le32_to_cpu(command->src_addr_hi),

			   le32_to_cpu(command->src_addr_lo),

			   le32_to_cpu(command->dst_addr_hi),

			   le32_to_cpu(command->dst_addr_lo));

			  le32_to_cpu(p_command->opcode),

			  le16_to_cpu(p_command->opcode_b),

			  le16_to_cpu(p_command->length_dw),

			  le32_to_cpu(p_command->src_addr_hi),

			  le32_to_cpu(p_command->src_addr_lo),

			  le32_to_cpu(p_command->dst_addr_hi),

			  le32_to_cpu(p_command->dst_addr_lo));



		return -EINVAL;

	}
@@ -459,13 +444,13 @@ qed_dmae_post_command(struct qed_hwfn *p_hwfn, 
		   NETIF_MSG_HW,

		   "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n",

		   idx_cmd,

		   le32_to_cpu(command->opcode),

		   le16_to_cpu(command->opcode_b),

		   le16_to_cpu(command->length_dw),

		   le32_to_cpu(command->src_addr_hi),

		   le32_to_cpu(command->src_addr_lo),

		   le32_to_cpu(command->dst_addr_hi),

		   le32_to_cpu(command->dst_addr_lo));

		   le32_to_cpu(p_command->opcode),

		   le16_to_cpu(p_command->opcode_b),

		   le16_to_cpu(p_command->length_dw),

		   le32_to_cpu(p_command->src_addr_hi),

		   le32_to_cpu(p_command->src_addr_lo),

		   le32_to_cpu(p_command->dst_addr_hi),

		   le32_to_cpu(p_command->dst_addr_lo));



	/* Copy the command to DMAE - need to do it before every call

	 * for source/dest address no reset.
@@ -475,7 +460,7 @@ qed_dmae_post_command(struct qed_hwfn *p_hwfn, 
	 */

	for (i = 0; i < DMAE_CMD_SIZE; i++) {

		u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?

			   *(((u32 *)command) + i) : 0;

			   *(((u32 *)p_command) + i) : 0;



		qed_wr(p_hwfn, p_ptt,

		       DMAE_REG_CMD_MEM +
@@ -483,9 +468,7 @@ qed_dmae_post_command(struct qed_hwfn *p_hwfn, 
		       (i * sizeof(u32)), data);

	}



	qed_wr(p_hwfn, p_ptt,

	       qed_dmae_idx_to_go_cmd(idx_cmd),

	       DMAE_GO_VALUE);

	qed_wr(p_hwfn, p_ptt, qed_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);



	return qed_status;

}
@@ -498,9 +481,7 @@ int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn) 
	u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;



	*p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,

				     sizeof(u32),

				     p_addr,

				     GFP_KERNEL);

				     sizeof(u32), p_addr, GFP_KERNEL);

	if (!*p_comp) {

		DP_NOTICE(p_hwfn, "Failed to allocate `p_completion_word'\n");

		goto err;
@@ -543,8 +524,7 @@ void qed_dmae_info_free(struct qed_hwfn *p_hwfn) 
		p_phys = p_hwfn->dmae_info.completion_word_phys_addr;

		dma_free_coherent(&p_hwfn->cdev->pdev->dev,

				  sizeof(u32),

				  p_hwfn->dmae_info.p_completion_word,

				  p_phys);

				  p_hwfn->dmae_info.p_completion_word, p_phys);

		p_hwfn->dmae_info.p_completion_word = NULL;

	}
@@ -552,8 +532,7 @@ void qed_dmae_info_free(struct qed_hwfn *p_hwfn) 
		p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;

		dma_free_coherent(&p_hwfn->cdev->pdev->dev,

				  sizeof(struct dmae_cmd),

				  p_hwfn->dmae_info.p_dmae_cmd,

				  p_phys);

				  p_hwfn->dmae_info.p_dmae_cmd, p_phys);

		p_hwfn->dmae_info.p_dmae_cmd = NULL;

	}
@@ -571,9 +550,7 @@ void qed_dmae_info_free(struct qed_hwfn *p_hwfn) 


static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn)

{

	u32 wait_cnt = 0;

	u32 wait_cnt_limit = 10000;



	u32 wait_cnt_limit = 10000, wait_cnt = 0;

	int qed_status = 0;



	barrier();
@@ -606,7 +583,7 @@ static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 
					  u64 dst_addr,

					  u8 src_type,

					  u8 dst_type,

					  u32 length)

					  u32 length_dw)

{

	dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;

	struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
@@ -624,7 +601,7 @@ static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 
		cmd->src_addr_lo = cpu_to_le32(lower_32_bits(phys));

		memcpy(&p_hwfn->dmae_info.p_intermediate_buffer[0],

		       (void *)(uintptr_t)src_addr,

		       length * sizeof(u32));

		       length_dw * sizeof(u32));

		break;

	default:

		return -EINVAL;
@@ -645,7 +622,7 @@ static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 
		return -EINVAL;

	}



	cmd->length_dw = cpu_to_le16((u16)length);

	cmd->length_dw = cpu_to_le16((u16)length_dw);



	qed_dmae_post_command(p_hwfn, p_ptt);
@@ -654,16 +631,14 @@ static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 
	if (qed_status) {

		DP_NOTICE(p_hwfn,

			  "qed_dmae_host2grc: Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x\n",

			  src_addr,

			  dst_addr,

			  length);

			  src_addr, dst_addr, length_dw);

		return qed_status;

	}



	if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT)

		memcpy((void *)(uintptr_t)(dst_addr),

		       &p_hwfn->dmae_info.p_intermediate_buffer[0],

		       length * sizeof(u32));

		       length_dw * sizeof(u32));



	return 0;

}
@@ -730,10 +705,7 @@ static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn, 
		if (qed_status) {

			DP_NOTICE(p_hwfn,

				  "qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n",

				  qed_status,

				  src_addr,

				  dst_addr,

				  length_cur);

				  qed_status, src_addr, dst_addr, length_cur);

			break;

		}

	}
@@ -743,10 +715,7 @@ static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn, 


int qed_dmae_host2grc(struct qed_hwfn *p_hwfn,

		      struct qed_ptt *p_ptt,

		      u64 source_addr,

		      u32 grc_addr,

		      u32 size_in_dwords,

		      u32 flags)

		  u64 source_addr, u32 grc_addr, u32 size_in_dwords, u32 flags)

{

	u32 grc_addr_in_dw = grc_addr / sizeof(u32);

	struct qed_dmae_params params;
@@ -768,8 +737,9 @@ int qed_dmae_host2grc(struct qed_hwfn *p_hwfn, 
	return rc;

}



int

qed_dmae_grc2host(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 grc_addr,

int qed_dmae_grc2host(struct qed_hwfn *p_hwfn,

		      struct qed_ptt *p_ptt,

		      u32 grc_addr,

		      dma_addr_t dest_addr, u32 size_in_dwords, u32 flags)

{

	u32 grc_addr_in_dw = grc_addr / sizeof(u32);
@@ -791,8 +761,7 @@ qed_dmae_grc2host(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 grc_addr, 
	return rc;

}



int

qed_dmae_host2host(struct qed_hwfn *p_hwfn,

int qed_dmae_host2host(struct qed_hwfn *p_hwfn,

		       struct qed_ptt *p_ptt,

		       dma_addr_t source_addr,

		       dma_addr_t dest_addr,

drivers/net/ethernet/qlogic/qed/qed_init_ops.c

+35 −58

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/qlogic/qed/qed_int.c

+46 −86

File changed.

Preview size limit exceeded, changes collapsed.

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