Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6 (a2724f28) · Commits · 戴 / test

drivers/net/3c59x.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -2942,6 +2942,9 @@ static void vortex_get_wol(struct net_device dev, struct ethtool_wolinfo wol)
		{
		struct vortex_private *vp = netdev_priv(dev);

		if (!VORTEX_PCI(vp))
		return;

		wol->supported = WAKE_MAGIC;

		wol->wolopts = 0;
		@@ -2952,6 +2955,10 @@ static void vortex_get_wol(struct net_device dev, struct ethtool_wolinfo wol)
		static int vortex_set_wol(struct net_device dev, struct ethtool_wolinfo wol)
		{
		struct vortex_private *vp = netdev_priv(dev);

		if (!VORTEX_PCI(vp))
		return -EOPNOTSUPP;

		if (wol->wolopts & ~WAKE_MAGIC)
		return -EINVAL;

		@@ -3201,6 +3208,9 @@ static void acpi_set_WOL(struct net_device *dev)
		return;
		}

		if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
		return;

		/* Change the power state to D3; RxEnable doesn't take effect. */
		pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
		}

drivers/net/atlx/atl1.c

+9 −2

Original line number	Diff line number	Diff line
		@@ -1251,6 +1251,12 @@ static void atl1_free_ring_resources(struct atl1_adapter *adapter)

		rrd_ring->desc = NULL;
		rrd_ring->dma = 0;

		adapter->cmb.dma = 0;
		adapter->cmb.cmb = NULL;

		adapter->smb.dma = 0;
		adapter->smb.smb = NULL;
		}

		static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
		@@ -2847,10 +2853,11 @@ static int atl1_resume(struct pci_dev *pdev)
		pci_enable_wake(pdev, PCI_D3cold, 0);

		atl1_reset_hw(&adapter->hw);
		adapter->cmb.cmb->int_stats = 0;

		if (netif_running(netdev))
		if (netif_running(netdev)) {
		adapter->cmb.cmb->int_stats = 0;
		atl1_up(adapter);
		}
		netif_device_attach(netdev);

		return 0;

drivers/net/e1000e/hw.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -57,6 +57,7 @@ enum e1e_registers {
		E1000_SCTL = 0x00024, /* SerDes Control - RW */
		E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
		E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
		E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
		E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
		E1000_FCT = 0x00030, /* Flow Control Type - RW */
		E1000_VET = 0x00038, /* VLAN Ether Type - RW */

drivers/net/e1000e/ich8lan.c

+164 −33

Original line number	Diff line number	Diff line
		@@ -105,6 +105,10 @@
		#define E1000_FEXTNVM_SW_CONFIG 1
		#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */

		#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
		#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
		#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3

		#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL

		#define E1000_ICH_RAR_ENTRIES 7
		@@ -125,6 +129,7 @@

		/* SMBus Address Phy Register */
		#define HV_SMB_ADDR PHY_REG(768, 26)
		#define HV_SMB_ADDR_MASK 0x007F
		#define HV_SMB_ADDR_PEC_EN 0x0200
		#define HV_SMB_ADDR_VALID 0x0080

		@@ -237,6 +242,8 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
		static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
		static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
		static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
		static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
		static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

		static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
		{
		@@ -272,7 +279,7 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
		static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
		{
		struct e1000_phy_info *phy = &hw->phy;
		u32 ctrl;
		u32 ctrl, fwsm;
		s32 ret_val = 0;

		phy->addr = 1;
		@@ -294,7 +301,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
		* disabled, then toggle the LANPHYPC Value bit to force
		* the interconnect to PCIe mode.
		*/
		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
		fwsm = er32(FWSM);
		if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
		ctrl = er32(CTRL);
		ctrl \|= E1000_CTRL_LANPHYPC_OVERRIDE;
		ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
		@@ -303,6 +311,13 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
		ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
		ew32(CTRL, ctrl);
		msleep(50);

		/*
		* Gate automatic PHY configuration by hardware on
		* non-managed 82579
		*/
		if (hw->mac.type == e1000_pch2lan)
		e1000_gate_hw_phy_config_ich8lan(hw, true);
		}

		/*
		@@ -315,6 +330,13 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
		if (ret_val)
		goto out;

		/* Ungate automatic PHY configuration on non-managed 82579 */
		if ((hw->mac.type == e1000_pch2lan) &&
		!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
		msleep(10);
		e1000_gate_hw_phy_config_ich8lan(hw, false);
		}

		phy->id = e1000_phy_unknown;
		ret_val = e1000e_get_phy_id(hw);
		if (ret_val)
		@@ -561,13 +583,10 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
		if (mac->type == e1000_ich8lan)
		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);

		/* Disable PHY configuration by hardware, config by software */
		if (mac->type == e1000_pch2lan) {
		u32 extcnf_ctrl = er32(EXTCNF_CTRL);

		extcnf_ctrl \|= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
		ew32(EXTCNF_CTRL, extcnf_ctrl);
		}
		/* Gate automatic PHY configuration by hardware on managed 82579 */
		if ((mac->type == e1000_pch2lan) &&
		(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
		e1000_gate_hw_phy_config_ich8lan(hw, true);

		return 0;
		}
		@@ -652,6 +671,12 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
		goto out;
		}

		if (hw->mac.type == e1000_pch2lan) {
		ret_val = e1000_k1_workaround_lv(hw);
		if (ret_val)
		goto out;
		}

		/*
		* Check if there was DownShift, must be checked
		* immediately after link-up
		@@ -894,6 +919,34 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
		return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
		}

		/**
		* e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
		* @hw: pointer to the HW structure
		*
		* Assumes semaphore already acquired.
		*
		**/
		static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
		{
		u16 phy_data;
		u32 strap = er32(STRAP);
		s32 ret_val = 0;

		strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;

		ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
		if (ret_val)
		goto out;

		phy_data &= ~HV_SMB_ADDR_MASK;
		phy_data \|= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
		phy_data \|= HV_SMB_ADDR_PEC_EN \| HV_SMB_ADDR_VALID;
		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);

		out:
		return ret_val;
		}

		/**
		* e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
		* @hw: pointer to the HW structure
		@@ -903,7 +956,6 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
		**/
		static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
		{
		struct e1000_adapter *adapter = hw->adapter;
		struct e1000_phy_info *phy = &hw->phy;
		u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
		s32 ret_val = 0;
		@@ -921,7 +973,8 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
		if (phy->type != e1000_phy_igp_3)
		return ret_val;

		if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
		if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) \|\|
		(hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
		break;
		}
		@@ -961,21 +1014,16 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
		cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
		cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;

		if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
		((hw->mac.type == e1000_pchlan) \|\|
		(hw->mac.type == e1000_pch2lan))) {
		if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
		(hw->mac.type == e1000_pchlan)) \|\|
		(hw->mac.type == e1000_pch2lan)) {
		/*
		* HW configures the SMBus address and LEDs when the
		* OEM and LCD Write Enable bits are set in the NVM.
		* When both NVM bits are cleared, SW will configure
		* them instead.
		*/
		data = er32(STRAP);
		data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
		reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
		reg_data \|= HV_SMB_ADDR_PEC_EN \| HV_SMB_ADDR_VALID;
		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
		reg_data);
		ret_val = e1000_write_smbus_addr(hw);
		if (ret_val)
		goto out;

		@@ -1440,10 +1488,6 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
		goto out;

		/* Enable jumbo frame workaround in the PHY */
		e1e_rphy(hw, PHY_REG(769, 20), &data);
		ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
		if (ret_val)
		goto out;
		e1e_rphy(hw, PHY_REG(769, 23), &data);
		data &= ~(0x7F << 5);
		data \|= (0x37 << 5);
		@@ -1452,7 +1496,6 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
		goto out;
		e1e_rphy(hw, PHY_REG(769, 16), &data);
		data &= ~(1 << 13);
		data \|= (1 << 12);
		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
		if (ret_val)
		goto out;
		@@ -1477,7 +1520,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)

		mac_reg = er32(RCTL);
		mac_reg &= ~E1000_RCTL_SECRC;
		ew32(FFLT_DBG, mac_reg);
		ew32(RCTL, mac_reg);

		ret_val = e1000e_read_kmrn_reg(hw,
		E1000_KMRNCTRLSTA_CTRL_OFFSET,
		@@ -1503,17 +1546,12 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
		goto out;

		/* Write PHY register values back to h/w defaults */
		e1e_rphy(hw, PHY_REG(769, 20), &data);
		ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
		if (ret_val)
		goto out;
		e1e_rphy(hw, PHY_REG(769, 23), &data);
		data &= ~(0x7F << 5);
		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
		if (ret_val)
		goto out;
		e1e_rphy(hw, PHY_REG(769, 16), &data);
		data &= ~(1 << 12);
		data \|= (1 << 13);
		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
		if (ret_val)
		@@ -1558,6 +1596,69 @@ out:
		return ret_val;
		}

		/**
		* e1000_k1_gig_workaround_lv - K1 Si workaround
		* @hw: pointer to the HW structure
		*
		* Workaround to set the K1 beacon duration for 82579 parts
		**/
		static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
		{
		s32 ret_val = 0;
		u16 status_reg = 0;
		u32 mac_reg;

		if (hw->mac.type != e1000_pch2lan)
		goto out;

		/* Set K1 beacon duration based on 1Gbps speed or otherwise */
		ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
		if (ret_val)
		goto out;

		if ((status_reg & (HV_M_STATUS_LINK_UP \| HV_M_STATUS_AUTONEG_COMPLETE))
		== (HV_M_STATUS_LINK_UP \| HV_M_STATUS_AUTONEG_COMPLETE)) {
		mac_reg = er32(FEXTNVM4);
		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;

		if (status_reg & HV_M_STATUS_SPEED_1000)
		mac_reg \|= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
		else
		mac_reg \|= E1000_FEXTNVM4_BEACON_DURATION_16USEC;

		ew32(FEXTNVM4, mac_reg);
		}

		out:
		return ret_val;
		}

		/**
		* e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
		* @hw: pointer to the HW structure
		* @gate: boolean set to true to gate, false to ungate
		*
		* Gate/ungate the automatic PHY configuration via hardware; perform
		* the configuration via software instead.
		**/
		static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
		{
		u32 extcnf_ctrl;

		if (hw->mac.type != e1000_pch2lan)
		return;

		extcnf_ctrl = er32(EXTCNF_CTRL);

		if (gate)
		extcnf_ctrl \|= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
		else
		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;

		ew32(EXTCNF_CTRL, extcnf_ctrl);
		return;
		}

		/**
		* e1000_lan_init_done_ich8lan - Check for PHY config completion
		* @hw: pointer to the HW structure
		@@ -1602,6 +1703,9 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
		if (e1000_check_reset_block(hw))
		goto out;

		/* Allow time for h/w to get to quiescent state after reset */
		msleep(10);

		/* Perform any necessary post-reset workarounds */
		switch (hw->mac.type) {
		case e1000_pchlan:
		@@ -1630,6 +1734,13 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
		/* Configure the LCD with the OEM bits in NVM */
		ret_val = e1000_oem_bits_config_ich8lan(hw, true);

		/* Ungate automatic PHY configuration on non-managed 82579 */
		if ((hw->mac.type == e1000_pch2lan) &&
		!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
		msleep(10);
		e1000_gate_hw_phy_config_ich8lan(hw, false);
		}

		out:
		return ret_val;
		}
		@@ -1646,6 +1757,11 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
		{
		s32 ret_val = 0;

		/* Gate automatic PHY configuration by hardware on non-managed 82579 */
		if ((hw->mac.type == e1000_pch2lan) &&
		!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
		e1000_gate_hw_phy_config_ich8lan(hw, true);

		ret_val = e1000e_phy_hw_reset_generic(hw);
		if (ret_val)
		goto out;
		@@ -2910,6 +3026,14 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
		* external PHY is reset.
		*/
		ctrl \|= E1000_CTRL_PHY_RST;

		/*
		* Gate automatic PHY configuration by hardware on
		* non-managed 82579
		*/
		if ((hw->mac.type == e1000_pch2lan) &&
		!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
		e1000_gate_hw_phy_config_ich8lan(hw, true);
		}
		ret_val = e1000_acquire_swflag_ich8lan(hw);
		e_dbg("Issuing a global reset to ich8lan\n");
		@@ -3460,13 +3584,20 @@ void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
		void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
		{
		u32 phy_ctrl;
		s32 ret_val;

		phy_ctrl = er32(PHY_CTRL);
		phy_ctrl \|= E1000_PHY_CTRL_D0A_LPLU \| E1000_PHY_CTRL_GBE_DISABLE;
		ew32(PHY_CTRL, phy_ctrl);

		if (hw->mac.type >= e1000_pchlan)
		e1000_phy_hw_reset_ich8lan(hw);
		if (hw->mac.type >= e1000_pchlan) {
		e1000_oem_bits_config_ich8lan(hw, true);
		ret_val = hw->phy.ops.acquire(hw);
		if (ret_val)
		return;
		e1000_write_smbus_addr(hw);
		hw->phy.ops.release(hw);
		}
		}

		/**

drivers/net/e1000e/netdev.c

+19 −10

Original line number	Diff line number	Diff line
		@@ -2704,6 +2704,16 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
		u32 psrctl = 0;
		u32 pages = 0;

		/* Workaround Si errata on 82579 - configure jumbo frame flow */
		if (hw->mac.type == e1000_pch2lan) {
		s32 ret_val;

		if (adapter->netdev->mtu > ETH_DATA_LEN)
		ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
		else
		ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
		}

		/* Program MC offset vector base */
		rctl = er32(RCTL);
		rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
		@@ -2744,16 +2754,6 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
		e1e_wphy(hw, 22, phy_data);
		}

		/* Workaround Si errata on 82579 - configure jumbo frame flow */
		if (hw->mac.type == e1000_pch2lan) {
		s32 ret_val;

		if (rctl & E1000_RCTL_LPE)
		ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
		else
		ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
		}

		/* Setup buffer sizes */
		rctl &= ~E1000_RCTL_SZ_4096;
		rctl \|= E1000_RCTL_BSEX;
		@@ -4833,6 +4833,15 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
		return -EINVAL;
		}

		/* Jumbo frame workaround on 82579 requires CRC be stripped */
		if ((adapter->hw.mac.type == e1000_pch2lan) &&
		!(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
		(new_mtu > ETH_DATA_LEN)) {
		e_err("Jumbo Frames not supported on 82579 when CRC "
		"stripping is disabled.\n");
		return -EINVAL;
		}

		/* 82573 Errata 17 */
		if (((adapter->hw.mac.type == e1000_82573) \|\|
		(adapter->hw.mac.type == e1000_82574)) &&

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