Commit a26ca6ad authored by Tina Zhang's avatar Tina Zhang Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Support BAR0 8-byte reads/writes 



GGTT is in BAR0 with 8 bytes aligned. With a qemu patch (commit:
38d49e8c1523d97d2191190d3f7b4ce7a0ab5aa3), VFIO can use 8-byte reads/
writes to access it.

This patch is to support the 8-byte GGTT reads/writes.

Ideally, we would like to support 8-byte reads/writes for the total BAR0.
But it needs more work for handling 8-byte MMIO reads/writes.

This patch can fix the issue caused by partial updating GGTT entry, during
guest booting up.

v3:
- Use intel_vgpu_get_bar_gpa() stead. (Zhenyu)
- Include all the GGTT checking logic in gtt_entry(). (Zhenyu)

v2:
- Limit to GGTT entry. (Zhenyu)

Signed-off-by: default avatarTina Zhang <tina.zhang@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 37ad4e68

drivers/gpu/drm/i915/gvt/kvmgt.c

+49 −2
Original line number Diff line number Diff line
@@ -733,6 +733,25 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf, 
	return ret == 0 ? count : ret;

}



static bool gtt_entry(struct mdev_device *mdev, loff_t *ppos)

{

	struct intel_vgpu *vgpu = mdev_get_drvdata(mdev);

	unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);

	struct intel_gvt *gvt = vgpu->gvt;

	int offset;



	/* Only allow MMIO GGTT entry access */

	if (index != PCI_BASE_ADDRESS_0)

		return false;



	offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) -

		intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);



	return (offset >= gvt->device_info.gtt_start_offset &&

		offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ?

			true : false;

}



static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf,

			size_t count, loff_t *ppos)

{
@@ -742,7 +761,21 @@ static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf, 
	while (count) {

		size_t filled;



		if (count >= 4 && !(*ppos % 4)) {

		/* Only support GGTT entry 8 bytes read */

		if (count >= 8 && !(*ppos % 8) &&

			gtt_entry(mdev, ppos)) {

			u64 val;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),

					ppos, false);

			if (ret <= 0)

				goto read_err;



			if (copy_to_user(buf, &val, sizeof(val)))

				goto read_err;



			filled = 8;

		} else if (count >= 4 && !(*ppos % 4)) {

			u32 val;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
@@ -802,7 +835,21 @@ static ssize_t intel_vgpu_write(struct mdev_device *mdev, 
	while (count) {

		size_t filled;



		if (count >= 4 && !(*ppos % 4)) {

		/* Only support GGTT entry 8 bytes write */

		if (count >= 8 && !(*ppos % 8) &&

			gtt_entry(mdev, ppos)) {

			u64 val;



			if (copy_from_user(&val, buf, sizeof(val)))

				goto write_err;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),

					ppos, true);

			if (ret <= 0)

				goto write_err;



			filled = 8;

		} else if (count >= 4 && !(*ppos % 4)) {

			u32 val;



			if (copy_from_user(&val, buf, sizeof(val)))

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