Commit a26a0298 authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Stephen Warren
Browse files

clk: tegra: Add flags to tegra_clk_periph()



We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent c1d1939c
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+6 −5
Original line number Diff line number Diff line
@@ -173,14 +173,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
static struct clk *_tegra_clk_register_periph(const char *name,
			const char **parent_names, int num_parents,
			struct tegra_clk_periph *periph,
			void __iomem *clk_base, u32 offset, bool div)
			void __iomem *clk_base, u32 offset, bool div,
			unsigned long flags)
{
	struct clk *clk;
	struct clk_init_data init;

	init.name = name;
	init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
	init.flags = div ? 0 : CLK_SET_RATE_PARENT;
	init.flags = flags;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

@@ -205,10 +206,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,
struct clk *tegra_clk_register_periph(const char *name,
		const char **parent_names, int num_parents,
		struct tegra_clk_periph *periph, void __iomem *clk_base,
		u32 offset)
		u32 offset, unsigned long flags)
{
	return _tegra_clk_register_periph(name, parent_names, num_parents,
			periph, clk_base, offset, true);
			periph, clk_base, offset, true, flags);
}

struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -217,5 +218,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
		u32 offset)
{
	return _tegra_clk_register_periph(name, parent_names, num_parents,
			periph, clk_base, offset, false);
			periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
}
+1 −1
Original line number Diff line number Diff line
@@ -1019,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
		data = &tegra_periph_clk_list[i];
		clk = tegra_clk_register_periph(data->name, data->parent_names,
				data->num_parents, &data->periph,
				clk_base, data->offset);
				clk_base, data->offset, data->flags);
		clk_register_clkdev(clk, data->con_id, data->dev_id);
		clks[data->clk_id] = clk;
	}
+1 −1
Original line number Diff line number Diff line
@@ -1668,7 +1668,7 @@ static void __init tegra30_periph_clk_init(void)
		data = &tegra_periph_clk_list[i];
		clk = tegra_clk_register_periph(data->name, data->parent_names,
				data->num_parents, &data->periph,
				clk_base, data->offset);
				clk_base, data->offset, data->flags);
		clk_register_clkdev(clk, data->con_id, data->dev_id);
		clks[data->clk_id] = clk;
	}
+6 −3
Original line number Diff line number Diff line
@@ -417,7 +417,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
struct clk *tegra_clk_register_periph(const char *name,
		const char **parent_names, int num_parents,
		struct tegra_clk_periph *periph, void __iomem *clk_base,
		u32 offset);
		u32 offset, unsigned long flags);
struct clk *tegra_clk_register_periph_nodiv(const char *name,
		const char **parent_names, int num_parents,
		struct tegra_clk_periph *periph, void __iomem *clk_base,
@@ -460,12 +460,14 @@ struct tegra_periph_init_data {
	u32 offset;
	const char *con_id;
	const char *dev_id;
	unsigned long flags;
};

#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
			_mux_shift, _mux_mask, _mux_flags, _div_shift,	\
			_div_width, _div_frac_width, _div_flags, _regs,	\
			_clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \
			_clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
			_flags) \
	{								\
		.name = _name,						\
		.clk_id = _clk_id,					\
@@ -480,6 +482,7 @@ struct tegra_periph_init_data {
		.offset = _offset,					\
		.con_id = _con_id,					\
		.dev_id = _dev_id,					\
		.flags = _flags						\
	}

#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
@@ -490,7 +493,7 @@ struct tegra_periph_init_data {
			_mux_shift, BIT(_mux_width) - 1, _mux_flags,	\
			_div_shift, _div_width, _div_frac_width, _div_flags, \
			_regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
			NULL)
			NULL, 0)

/**
 * struct clk_super_mux - super clock