Commit a24d025a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (29 commits)
  MIPS: Call oops_enter, oops_exit in die
  staging/octeon: Software should check the checksum of no tcp/udp packets
  MIPS: Octeon: Enable C0_UserLocal probing.
  MIPS: No branches in delay slots for huge pages in handle_tlbl
  MIPS: Don't clobber CP0_STATUS value for CONFIG_MIPS_MT_SMTC
  MIPS: Octeon: Select CONFIG_HOLES_IN_ZONE
  MIPS: PM: Use struct syscore_ops instead of sysdevs for PM (v2)
  MIPS: Compat: Use 32-bit wrapper for compat_sys_futex.
  MIPS: Do not use EXTRA_CFLAGS
  MIPS: Alchemy: DB1200: Disable cascade IRQ in handler
  SERIAL: Lantiq: Set timeout in uart_port
  MIPS: Lantiq: Fix setting the PCI bus speed on AR9
  MIPS: Lantiq: Fix external interrupt sources
  MIPS: tlbex: Fix build error in R3000 code.
  MIPS: Alchemy: Include Au1100 in PM code.
  MIPS: Alchemy: Fix typo in MAC0 registration
  MIPS: MSP71xx: Fix build error.
  MIPS: Handle __put_user() sleeping.
  MIPS: Allow forced irq threading
  MIPS: i8259: Mark cascade interrupt non-threaded
  ...
parents 3ee72ca9 8742cd23

arch/mips/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ config MIPS 
	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select HAVE_ARCH_JUMP_LABEL

	select IRQ_FORCED_THREADING



menu "Machine selection"
@@ -722,6 +723,7 @@ config CAVIUM_OCTEON_SIMULATOR 
	select SYS_SUPPORTS_HIGHMEM

	select SYS_SUPPORTS_HOTPLUG_CPU

	select SYS_HAS_CPU_CAVIUM_OCTEON

	select HOLES_IN_ZONE

	help

	  The Octeon simulator is software performance model of the Cavium

	  Octeon Processor. It supports simulating Octeon processors on x86
@@ -744,6 +746,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD 
	select ZONE_DMA32

	select USB_ARCH_HAS_OHCI

	select USB_ARCH_HAS_EHCI

	select HOLES_IN_ZONE

	help

	  This option supports all of the Octeon reference boards from Cavium

	  Networks. It builds a kernel that dynamically determines the Octeon
@@ -973,6 +976,9 @@ config ISA_DMA_API 
config GENERIC_GPIO

	bool



config HOLES_IN_ZONE

	bool



#

# Endianess selection.  Sufficiently obscure so many users don't know what to

# answer,so we try hard to limit the available choices.  Also the use of a

arch/mips/alchemy/common/platform.c

+1 −1
Original line number Diff line number Diff line
@@ -492,7 +492,7 @@ static void __init alchemy_setup_macs(int ctype) 
		memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);



	ret = platform_device_register(&au1xxx_eth0_device);

	if (!ret)

	if (ret)

		printk(KERN_INFO "Alchemy: failed to register MAC0\n");

arch/mips/alchemy/common/power.c

+14 −8
Original line number Diff line number Diff line
@@ -158,15 +158,21 @@ static void restore_core_regs(void) 


void au_sleep(void)

{

	int cpuid = alchemy_get_cputype();

	if (cpuid != ALCHEMY_CPU_UNKNOWN) {

	save_core_regs();

		if (cpuid <= ALCHEMY_CPU_AU1500)



	switch (alchemy_get_cputype()) {

	case ALCHEMY_CPU_AU1000:

	case ALCHEMY_CPU_AU1500:

	case ALCHEMY_CPU_AU1100:

		alchemy_sleep_au1000();

		else if (cpuid <= ALCHEMY_CPU_AU1200)

		break;

	case ALCHEMY_CPU_AU1550:

	case ALCHEMY_CPU_AU1200:

		alchemy_sleep_au1550();

		restore_core_regs();

		break;

	}



	restore_core_regs();

}



#endif	/* CONFIG_PM */

arch/mips/alchemy/devboards/bcsr.c

+4 −0
Original line number Diff line number Diff line
@@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) 
{

	unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);



	disable_irq_nosync(irq);



	for ( ; bisr; bisr &= bisr - 1)

		generic_handle_irq(bcsr_csc_base + __ffs(bisr));



	enable_irq(irq);

}



/* NOTE: both the enable and mask bits must be cleared, otherwise the

arch/mips/alchemy/devboards/db1200/setup.c

+0 −7
Original line number Diff line number Diff line
@@ -23,13 +23,6 @@ void __init board_setup(void) 
	unsigned long freq0, clksrc, div, pfc;

	unsigned short whoami;



	/* Set Config[OD] (disable overlapping bus transaction):

	 * This gets rid of a _lot_ of spurious interrupts (especially

	 * wrt. IDE); but incurs ~10% performance hit in some

	 * cpu-bound applications.

	 */

	set_c0_config(1 << 19);



	bcsr_init(DB1200_BCSR_PHYS_ADDR,

		  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);

CRA Git | Maintained and supported by SUSTech CRA and CCSE