Commit a211da9c authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/gt: Make timeslicing an explicit engine property 



In order to allow userspace to rely on timeslicing to reorder their
batches, we must support preemption of those user batches. Declare
timeslicing as an explicit property that is a combination of having the
kernel support and HW support.

Suggested-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 8ee36e04 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200501122249.12417-1-chris@chris-wilson.co.uk
parent 3b55cdeb

drivers/gpu/drm/i915/gt/intel_engine.h

+0 −9
Original line number Diff line number Diff line
@@ -332,13 +332,4 @@ intel_engine_has_preempt_reset(const struct intel_engine_cs *engine) 
	return intel_engine_has_preemption(engine);

}



static inline bool

intel_engine_has_timeslices(const struct intel_engine_cs *engine)

{

	if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))

		return false;



	return intel_engine_has_semaphores(engine);

}



#endif /* _INTEL_RINGBUFFER_H_ */

drivers/gpu/drm/i915/gt/intel_engine_types.h

+14 −4
Original line number Diff line number Diff line
@@ -492,10 +492,11 @@ struct intel_engine_cs { 
#define I915_ENGINE_SUPPORTS_STATS   BIT(1)

#define I915_ENGINE_HAS_PREEMPTION   BIT(2)

#define I915_ENGINE_HAS_SEMAPHORES   BIT(3)

#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)

#define I915_ENGINE_IS_VIRTUAL       BIT(5)

#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)

#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)

#define I915_ENGINE_HAS_TIMESLICES   BIT(4)

#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)

#define I915_ENGINE_IS_VIRTUAL       BIT(6)

#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)

#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)

	unsigned int flags;



	/*
@@ -593,6 +594,15 @@ intel_engine_has_semaphores(const struct intel_engine_cs *engine) 
	return engine->flags & I915_ENGINE_HAS_SEMAPHORES;

}



static inline bool

intel_engine_has_timeslices(const struct intel_engine_cs *engine)

{

	if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))

		return false;



	return engine->flags & I915_ENGINE_HAS_TIMESLICES;

}



static inline bool

intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)

{

drivers/gpu/drm/i915/gt/intel_lrc.c

+4 −1
Original line number Diff line number Diff line
@@ -4801,8 +4801,11 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine) 
	engine->flags |= I915_ENGINE_SUPPORTS_STATS;

	if (!intel_vgpu_active(engine->i915)) {

		engine->flags |= I915_ENGINE_HAS_SEMAPHORES;

		if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))

		if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {

			engine->flags |= I915_ENGINE_HAS_PREEMPTION;

			if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))

				engine->flags |= I915_ENGINE_HAS_TIMESLICES;

		}

	}



	if (INTEL_GEN(engine->i915) >= 12)

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