Commit a1ef8bad authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/disp/gm200-: fix NV_PDISP_SOR_HDMI2_CTRL(n) selection 



This is a SOR register, and not indexed by the bound head.

Fixes display not coming up on high-bandwidth HDMI displays under a
number of configurations.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent dc455f4c

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c

+2 −2
Original line number Diff line number Diff line
@@ -27,10 +27,10 @@ void 
gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc)

{

	struct nvkm_device *device = ior->disp->engine.subdev.device;

	const u32 hoff = head * 0x800;

	const u32 soff = nv50_ior_base(ior);

	const u32 ctrl = scdc & 0x3;



	nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl);

	nvkm_mask(device, 0x61c5bc + soff, 0x00000003, ctrl);



	ior->tmds.high_speed = !!(scdc & 0x2);

}

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