Commit a1cf573e authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Herbert Xu
Browse files

crypto: caam - select DMA address size at runtime 



i.MX8 mScale SoC still use 32-bit addresses in its CAAM implmentation,
so we can't rely on sizeof(dma_addr_t) to detemine CAAM pointer
size. Convert the code to query CTPR and MCFGR for that during driver
probing.

Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Cc: Chris Spencer <christopher.spencer@sea.co.uk>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Horia Geantă <horia.geanta@nxp.com>
Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent dff36801

drivers/crypto/caam/caampkc.c

+4 −4
Original line number Diff line number Diff line
@@ -17,13 +17,13 @@ 
#include "sg_sw_sec4.h"

#include "caampkc.h"



#define DESC_RSA_PUB_LEN	(2 * CAAM_CMD_SZ + sizeof(struct rsa_pub_pdb))

#define DESC_RSA_PUB_LEN	(2 * CAAM_CMD_SZ + SIZEOF_RSA_PUB_PDB)

#define DESC_RSA_PRIV_F1_LEN	(2 * CAAM_CMD_SZ + \

				 sizeof(struct rsa_priv_f1_pdb))

				 SIZEOF_RSA_PRIV_F1_PDB)

#define DESC_RSA_PRIV_F2_LEN	(2 * CAAM_CMD_SZ + \

				 sizeof(struct rsa_priv_f2_pdb))

				 SIZEOF_RSA_PRIV_F2_PDB)

#define DESC_RSA_PRIV_F3_LEN	(2 * CAAM_CMD_SZ + \

				 sizeof(struct rsa_priv_f3_pdb))

				 SIZEOF_RSA_PRIV_F3_PDB)

#define CAAM_RSA_MAX_INPUT_SIZE	512 /* for a 4096-bit modulus */



/* buffer filled with zeros, used for padding */

drivers/crypto/caam/ctrl.c

+4 −1
Original line number Diff line number Diff line
@@ -602,7 +602,10 @@ static int caam_probe(struct platform_device *pdev) 
	caam_imx = (bool)imx_soc_match;



	comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);

	caam_ptr_sz = sizeof(dma_addr_t);

	if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)

		caam_ptr_sz = sizeof(u64);

	else

		caam_ptr_sz = sizeof(u32);

	caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);

	ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);

drivers/crypto/caam/desc_constr.h

+8 −2
Original line number Diff line number Diff line
@@ -136,9 +136,15 @@ static inline void init_job_desc_pdb(u32 * const desc, u32 options, 


static inline void append_ptr(u32 * const desc, dma_addr_t ptr)

{

	if (caam_ptr_sz == sizeof(dma_addr_t)) {

		dma_addr_t *offset = (dma_addr_t *)desc_end(desc);



		*offset = cpu_to_caam_dma(ptr);

	} else {

		u32 *offset = (u32 *)desc_end(desc);



		*offset = cpu_to_caam_dma(ptr);

	}



	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +

				CAAM_PTR_SZ / CAAM_CMD_SZ);

drivers/crypto/caam/intern.h

+1 −1
Original line number Diff line number Diff line
@@ -219,7 +219,7 @@ static inline u64 caam_get_dma_mask(struct device *dev) 
{

	struct device_node *nprop = dev->of_node;



	if (sizeof(dma_addr_t) != sizeof(u64))

	if (caam_ptr_sz != sizeof(u64))

		return DMA_BIT_MASK(32);



	if (caam_dpaa2)

drivers/crypto/caam/pdb.h

+12 −4
Original line number Diff line number Diff line
@@ -512,7 +512,9 @@ struct rsa_pub_pdb { 
	dma_addr_t	n_dma;

	dma_addr_t	e_dma;

	u32		f_len;

} __packed;

};



#define SIZEOF_RSA_PUB_PDB	(2 * sizeof(u32) + 4 * caam_ptr_sz)



/**

 * RSA Decrypt PDB - Private Key Form #1
@@ -528,7 +530,9 @@ struct rsa_priv_f1_pdb { 
	dma_addr_t	f_dma;

	dma_addr_t	n_dma;

	dma_addr_t	d_dma;

} __packed;

};



#define SIZEOF_RSA_PRIV_F1_PDB	(sizeof(u32) + 4 * caam_ptr_sz)



/**

 * RSA Decrypt PDB - Private Key Form #2
@@ -554,7 +558,9 @@ struct rsa_priv_f2_pdb { 
	dma_addr_t	tmp1_dma;

	dma_addr_t	tmp2_dma;

	u32		p_q_len;

} __packed;

};



#define SIZEOF_RSA_PRIV_F2_PDB	(2 * sizeof(u32) + 7 * caam_ptr_sz)



/**

 * RSA Decrypt PDB - Private Key Form #3
@@ -586,6 +592,8 @@ struct rsa_priv_f3_pdb { 
	dma_addr_t	tmp1_dma;

	dma_addr_t	tmp2_dma;

	u32		p_q_len;

} __packed;

};



#define SIZEOF_RSA_PRIV_F3_PDB	(2 * sizeof(u32) + 9 * caam_ptr_sz)



#endif

CRA Git | Maintained and supported by SUSTech CRA and CCSE