drm/i915: Remove lrc default desc from GEM context (a1c9ca22) · Commits · 戴 / test

drivers/gpu/drm/i915/gem/i915_gem_context.c

+2 −26

Original line number	Diff line number	Diff line
		@@ -397,30 +397,6 @@ static void context_close(struct i915_gem_context *ctx)
		i915_gem_context_put(ctx);
		}

		static u32 default_desc_template(const struct drm_i915_private *i915,
		const struct i915_address_space *vm)
		{
		u32 address_mode;
		u32 desc;

		desc = GEN8_CTX_VALID \| GEN8_CTX_PRIVILEGE;

		address_mode = INTEL_LEGACY_32B_CONTEXT;
		if (vm && i915_vm_is_4lvl(vm))
		address_mode = INTEL_LEGACY_64B_CONTEXT;
		desc \|= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;

		if (IS_GEN(i915, 8))
		desc \|= GEN8_CTX_L3LLC_COHERENT;

		/* TODO: WaDisableLiteRestore when we start using semaphore
		* signalling between Command Streamers
		* ring->ctx_desc_template \|= GEN8_CTX_FORCE_RESTORE;
		*/

		return desc;
		}

		static struct i915_gem_context *
		__create_context(struct drm_i915_private *i915)
		{
		@@ -459,7 +435,6 @@ __create_context(struct drm_i915_private *i915)
		i915_gem_context_set_recoverable(ctx);

		ctx->ring_size = 4 * PAGE_SIZE;
		ctx->desc_template = default_desc_template(i915, NULL);

		for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
		ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
		@@ -478,8 +453,9 @@ __set_ppgtt(struct i915_gem_context ctx, struct i915_address_space vm)
		struct i915_gem_engines_iter it;
		struct intel_context *ce;

		GEM_BUG_ON(old && i915_vm_is_4lvl(vm) != i915_vm_is_4lvl(old));

		ctx->vm = i915_vm_get(vm);
		ctx->desc_template = default_desc_template(ctx->i915, vm);

		for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
		i915_vm_put(ce->vm);

+0 −2

Original line number	Diff line number	Diff line
		@@ -171,8 +171,6 @@ struct i915_gem_context {

		/** ring_size: size for allocating the per-engine ring buffer */
		u32 ring_size;
		/** desc_template: invariant fields for the HW context descriptor */
		u32 desc_template;

		/** guilty_count: How many times this context has caused a GPU hang. */
		atomic_t guilty_count;

+8 −4

Original line number	Diff line number	Diff line
		@@ -417,13 +417,17 @@ lrc_descriptor(struct intel_context ce, struct intel_engine_cs engine)
		BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
		BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));

		desc = ctx->desc_template; /* bits 0-11 */
		GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
		desc = INTEL_LEGACY_32B_CONTEXT;
		if (i915_vm_is_4lvl(ce->vm))
		desc = INTEL_LEGACY_64B_CONTEXT;
		desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;

		desc \|= GEN8_CTX_VALID \| GEN8_CTX_PRIVILEGE;
		if (IS_GEN(engine->i915, 8))
		desc \|= GEN8_CTX_L3LLC_COHERENT;

		desc \|= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
		/* bits 12-31 */
		GEM_BUG_ON(desc & GENMASK_ULL(63, 32));

		/*
		* The following 32bits are copied into the OA reports (dword 2).
		* Consider updating oa_get_render_ctx_id in i915_perf.c when changing

+0 −3

Original line number	Diff line number	Diff line
		@@ -291,9 +291,6 @@ shadow_context_descriptor_update(struct intel_context *ce,
		* Update bits 0-11 of the context descriptor which includes flags
		* like GEN8_CTX_* cached in desc_template
		*/
		desc &= U64_MAX << 12;
		desc \|= ce->gem_context->desc_template & ((1ULL << 12) - 1);

		desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
		desc \|= workload->ctx_desc.addressing_mode <<
		GEN8_CTX_ADDRESSING_MODE_SHIFT;