Commit a1c5f151 authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Lucas De Marchi
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drm/i915/tgl: Update DPLL clock reference register 



This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.

Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-22-lucas.demarchi@intel.com
parent 36ca5335

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+6 −2
Original line number Diff line number Diff line
@@ -2597,8 +2597,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, 
	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |

		 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |

		 DPLL_CFGCR1_KDIV(pll_params.kdiv) |

		 DPLL_CFGCR1_PDIV(pll_params.pdiv) |

		 DPLL_CFGCR1_CENTRAL_FREQ_8400;

		 DPLL_CFGCR1_PDIV(pll_params.pdiv);



	if (INTEL_GEN(dev_priv) >= 12)

		cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;

	else

		cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;



	memset(pll_state, 0, sizeof(*pll_state));

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -9944,6 +9944,7 @@ enum skl_power_gate { 
#define  DPLL_CFGCR1_PDIV_7		(8 << 2)

#define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)

#define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)

#define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)

#define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)



#define _ICL_DPLL0_CFGCR0		0x164000

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