Commit a1ab41eb authored by Gilad Ben-Yossef's avatar Gilad Ben-Yossef Committed by Greg Kroah-Hartman
Browse files

staging: ccree: stdint to kernel types conversion 



Move from stdint style int_t/uint_t to kernel style u/s types.

Signed-off-by: default avatarGilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b4573c90

drivers/staging/ccree/cc_crypto_ctx.h

+35 −40
Original line number Diff line number Diff line
@@ -18,12 +18,7 @@ 
#ifndef _CC_CRYPTO_CTX_H_

#define _CC_CRYPTO_CTX_H_



#ifdef __KERNEL__

#include <linux/types.h>

#define INT32_MAX 0x7FFFFFFFL

#else

#include <stdint.h>

#endif





#ifndef max
@@ -113,7 +108,7 @@ enum drv_engine_type { 
	DRV_ENGINE_HASH = 3,

	DRV_ENGINE_RC4 = 4,

	DRV_ENGINE_DOUT = 5,

	DRV_ENGINE_RESERVE32B = INT32_MAX,

	DRV_ENGINE_RESERVE32B = S32_MAX,

};



enum drv_crypto_alg {
@@ -126,7 +121,7 @@ enum drv_crypto_alg { 
	DRV_CRYPTO_ALG_AEAD = 5,

	DRV_CRYPTO_ALG_BYPASS = 6,

	DRV_CRYPTO_ALG_NUM = 7,

	DRV_CRYPTO_ALG_RESERVE32B = INT32_MAX

	DRV_CRYPTO_ALG_RESERVE32B = S32_MAX

};



enum drv_crypto_direction {
@@ -134,7 +129,7 @@ enum drv_crypto_direction { 
	DRV_CRYPTO_DIRECTION_ENCRYPT = 0,

	DRV_CRYPTO_DIRECTION_DECRYPT = 1,

	DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3,

	DRV_CRYPTO_DIRECTION_RESERVE32B = INT32_MAX

	DRV_CRYPTO_DIRECTION_RESERVE32B = S32_MAX

};



enum drv_cipher_mode {
@@ -152,7 +147,7 @@ enum drv_cipher_mode { 
	DRV_CIPHER_GCTR = 12,

	DRV_CIPHER_ESSIV = 13,

	DRV_CIPHER_BITLOCKER = 14,

	DRV_CIPHER_RESERVE32B = INT32_MAX

	DRV_CIPHER_RESERVE32B = S32_MAX

};



enum drv_hash_mode {
@@ -167,7 +162,7 @@ enum drv_hash_mode { 
	DRV_HASH_XCBC_MAC = 7,

	DRV_HASH_CMAC = 8,

	DRV_HASH_MODE_NUM = 9,

	DRV_HASH_RESERVE32B = INT32_MAX

	DRV_HASH_RESERVE32B = S32_MAX

};



enum drv_hash_hw_mode {
@@ -178,7 +173,7 @@ enum drv_hash_hw_mode { 
	DRV_HASH_HW_SHA512 = 4,

	DRV_HASH_HW_SHA384 = 12,

	DRV_HASH_HW_GHASH = 6,

	DRV_HASH_HW_RESERVE32B = INT32_MAX

	DRV_HASH_HW_RESERVE32B = S32_MAX

};



enum drv_multi2_mode {
@@ -186,7 +181,7 @@ enum drv_multi2_mode { 
	DRV_MULTI2_ECB = 0,

	DRV_MULTI2_CBC = 1,

	DRV_MULTI2_OFB = 2,

	DRV_MULTI2_RESERVE32B = INT32_MAX

	DRV_MULTI2_RESERVE32B = S32_MAX

};
@@ -201,13 +196,13 @@ enum drv_crypto_key_type { 
	DRV_APPLET_KEY = 4,		/* NA */

	DRV_PLATFORM_KEY = 5,		/* 0x101 */

	DRV_CUSTOMER_KEY = 6,		/* 0x110 */

	DRV_END_OF_KEYS = INT32_MAX,

	DRV_END_OF_KEYS = S32_MAX,

};



enum drv_crypto_padding_type {

	DRV_PADDING_NONE = 0,

	DRV_PADDING_PKCS7 = 1,

	DRV_PADDING_RESERVE32B = INT32_MAX

	DRV_PADDING_RESERVE32B = S32_MAX

};



/*******************************************************************/
@@ -223,9 +218,9 @@ struct drv_ctx_generic { 
struct drv_ctx_hash {

	enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HASH */

	enum drv_hash_mode mode;

	uint8_t digest[CC_DIGEST_SIZE_MAX];

	u8 digest[CC_DIGEST_SIZE_MAX];

	/* reserve to end of allocated context size */

	uint8_t reserved[CC_CTX_SIZE - 2 * sizeof(uint32_t) -

	u8 reserved[CC_CTX_SIZE - 2 * sizeof(u32) -

			CC_DIGEST_SIZE_MAX];

};
@@ -234,11 +229,11 @@ struct drv_ctx_hash { 
struct drv_ctx_hmac {

	enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HMAC */

	enum drv_hash_mode mode;

	uint8_t digest[CC_DIGEST_SIZE_MAX];

	uint32_t k0[CC_HMAC_BLOCK_SIZE_MAX/sizeof(uint32_t)];

	uint32_t k0_size;

	u8 digest[CC_DIGEST_SIZE_MAX];

	u32 k0[CC_HMAC_BLOCK_SIZE_MAX/sizeof(u32)];

	u32 k0_size;

	/* reserve to end of allocated context size */

	uint8_t reserved[CC_CTX_SIZE - 3 * sizeof(uint32_t) -

	u8 reserved[CC_CTX_SIZE - 3 * sizeof(u32) -

			CC_DIGEST_SIZE_MAX - CC_HMAC_BLOCK_SIZE_MAX];

};
@@ -248,19 +243,19 @@ struct drv_ctx_cipher { 
	enum drv_crypto_direction direction;

	enum drv_crypto_key_type crypto_key_type;

	enum drv_crypto_padding_type padding_type;

	uint32_t key_size; /* numeric value in bytes   */

	uint32_t data_unit_size; /* required for XTS */

	u32 key_size; /* numeric value in bytes   */

	u32 data_unit_size; /* required for XTS */

	/* block_state is the AES engine block state.

	*  It is used by the host to pass IV or counter at initialization.

	*  It is used by SeP for intermediate block chaining state and for

	*  returning MAC algorithms results.           */

	uint8_t block_state[CC_AES_BLOCK_SIZE];

	uint8_t key[CC_AES_KEY_SIZE_MAX];

	uint8_t xex_key[CC_AES_KEY_SIZE_MAX];

	u8 block_state[CC_AES_BLOCK_SIZE];

	u8 key[CC_AES_KEY_SIZE_MAX];

	u8 xex_key[CC_AES_KEY_SIZE_MAX];

	/* reserve to end of allocated context size */

	uint32_t reserved[CC_DRV_CTX_SIZE_WORDS - 7 -

		CC_AES_BLOCK_SIZE/sizeof(uint32_t) - 2 *

		(CC_AES_KEY_SIZE_MAX/sizeof(uint32_t))];

	u32 reserved[CC_DRV_CTX_SIZE_WORDS - 7 -

		CC_AES_BLOCK_SIZE/sizeof(u32) - 2 *

		(CC_AES_KEY_SIZE_MAX/sizeof(u32))];

};



/* authentication and encryption with associated data class */
@@ -268,20 +263,20 @@ struct drv_ctx_aead { 
	enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */

	enum drv_cipher_mode mode;

	enum drv_crypto_direction direction;

	uint32_t key_size; /* numeric value in bytes   */

	uint32_t nonce_size; /* nonce size (octets) */

	uint32_t header_size; /* finit additional data size (octets) */

	uint32_t text_size; /* finit text data size (octets) */

	uint32_t tag_size; /* mac size, element of {4, 6, 8, 10, 12, 14, 16} */

	u32 key_size; /* numeric value in bytes   */

	u32 nonce_size; /* nonce size (octets) */

	u32 header_size; /* finit additional data size (octets) */

	u32 text_size; /* finit text data size (octets) */

	u32 tag_size; /* mac size, element of {4, 6, 8, 10, 12, 14, 16} */

	/* block_state1/2 is the AES engine block state */

	uint8_t block_state[CC_AES_BLOCK_SIZE];

	uint8_t mac_state[CC_AES_BLOCK_SIZE]; /* MAC result */

	uint8_t nonce[CC_AES_BLOCK_SIZE]; /* nonce buffer */

	uint8_t key[CC_AES_KEY_SIZE_MAX];

	u8 block_state[CC_AES_BLOCK_SIZE];

	u8 mac_state[CC_AES_BLOCK_SIZE]; /* MAC result */

	u8 nonce[CC_AES_BLOCK_SIZE]; /* nonce buffer */

	u8 key[CC_AES_KEY_SIZE_MAX];

	/* reserve to end of allocated context size */

	uint32_t reserved[CC_DRV_CTX_SIZE_WORDS - 8 -

		3 * (CC_AES_BLOCK_SIZE/sizeof(uint32_t)) -

		CC_AES_KEY_SIZE_MAX/sizeof(uint32_t)];

	u32 reserved[CC_DRV_CTX_SIZE_WORDS - 8 -

		3 * (CC_AES_BLOCK_SIZE/sizeof(u32)) -

		CC_AES_KEY_SIZE_MAX/sizeof(u32)];

};



/*******************************************************************/

drivers/staging/ccree/cc_hw_queue_defs.h

+25 −32
Original line number Diff line number Diff line
@@ -17,18 +17,11 @@ 
#ifndef __CC_HW_QUEUE_DEFS_H__

#define __CC_HW_QUEUE_DEFS_H__



#include <linux/types.h>



#include "cc_regs.h"

#include "dx_crys_kernel.h"



#ifdef __KERNEL__

#include <linux/types.h>

#define UINT32_MAX 0xFFFFFFFFL

#define INT32_MAX  0x7FFFFFFFL

#define UINT16_MAX 0xFFFFL

#else

#include <stdint.h>

#endif



/******************************************************************************

*                        	DEFINITIONS

******************************************************************************/
@@ -48,7 +41,7 @@ 
******************************************************************************/



typedef struct HwDesc {

	uint32_t word[HW_DESC_SIZE_WORDS];

	u32 word[HW_DESC_SIZE_WORDS];

} HwDesc_s;



typedef enum DescDirection {
@@ -56,7 +49,7 @@ typedef enum DescDirection { 
	DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,

	DESC_DIRECTION_DECRYPT_DECRYPT = 1,

	DESC_DIRECTION_DECRYPT_ENCRYPT = 3,

	DESC_DIRECTION_END = INT32_MAX,

	DESC_DIRECTION_END = S32_MAX,

}DescDirection_t;



typedef enum DmaMode {
@@ -66,7 +59,7 @@ typedef enum DmaMode { 
	DMA_DLLI		= 2,

	DMA_MLLI		= 3,

	DmaMode_OPTIONTS,

	DmaMode_END 		= INT32_MAX,

	DmaMode_END 		= S32_MAX,

}DmaMode_t;



typedef enum FlowMode {
@@ -105,7 +98,7 @@ typedef enum FlowMode { 
	S_HASH_to_DOUT		= 43,

	SET_FLOW_ID		= 44,

	FlowMode_OPTIONTS,

	FlowMode_END = INT32_MAX,

	FlowMode_END = S32_MAX,

}FlowMode_t;



typedef enum TunnelOp {
@@ -113,7 +106,7 @@ typedef enum TunnelOp { 
	TUNNEL_OFF = 0,

	TUNNEL_ON = 1,

	TunnelOp_OPTIONS,

	TunnelOp_END = INT32_MAX,

	TunnelOp_END = S32_MAX,

} TunnelOp_t;



typedef enum SetupOp {
@@ -128,14 +121,14 @@ typedef enum SetupOp { 
	SETUP_WRITE_STATE2	= 10,

	SETUP_WRITE_STATE3	= 11,

	setupOp_OPTIONTS,

	setupOp_END = INT32_MAX,

	setupOp_END = S32_MAX,

}SetupOp_t;



enum AesMacSelector {

	AES_SK = 1,

	AES_CMAC_INIT = 2,

	AES_CMAC_SIZE0 = 3,

	AesMacEnd = INT32_MAX,

	AesMacEnd = S32_MAX,

};



#define HW_KEY_MASK_CIPHER_DO 	  0x3
@@ -156,21 +149,21 @@ typedef enum HwCryptoKey { 
	KFDE1_KEY = 9,			/* 0x1001 */

	KFDE2_KEY = 10,			/* 0x1010 */

	KFDE3_KEY = 11,			/* 0x1011 */

	END_OF_KEYS = INT32_MAX,

	END_OF_KEYS = S32_MAX,

}HwCryptoKey_t;



typedef enum HwAesKeySize {

	AES_128_KEY = 0,

	AES_192_KEY = 1,

	AES_256_KEY = 2,

	END_OF_AES_KEYS = INT32_MAX,

	END_OF_AES_KEYS = S32_MAX,

}HwAesKeySize_t;



typedef enum HwDesKeySize {

	DES_ONE_KEY = 0,

	DES_TWO_KEYS = 1,

	DES_THREE_KEYS = 2,

	END_OF_DES_KEYS = INT32_MAX,

	END_OF_DES_KEYS = S32_MAX,

}HwDesKeySize_t;



/*****************************/
@@ -210,7 +203,7 @@ typedef enum HwDesKeySize { 
	} while (0)





#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&UINT16_MAX)

#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&U16_MAX)



/*!

 * This macro sets the DIN field of a HW descriptors
@@ -223,7 +216,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DIN_TYPE(pDesc, dmaMode, dinAdr, dinSize, axiNs)								\

	do {		                                                                                        		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (dinAdr)&UINT32_MAX );			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (dinAdr)&U32_MAX );			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DIN_ADDR_HIGH, (pDesc)->word[5], MSB64(dinAdr) );		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], (dmaMode));			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));				\
@@ -241,7 +234,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DIN_NO_DMA(pDesc, dinAdr, dinSize)									\

	do {		                                                                                        	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (u32)(dinAdr));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));			\

	} while (0)
@@ -256,7 +249,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DIN_SRAM(pDesc, dinAdr, dinSize)									\

	do {		                                                                                        	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (u32)(dinAdr));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM);		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));			\

	} while (0)
@@ -269,7 +262,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DIN_CONST(pDesc, val, dinSize)									\

	do {		                                                                                        	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(val));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (u32)(val));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_CONST_VALUE, (pDesc)->word[1], 1);			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM);		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));			\
@@ -296,7 +289,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DOUT_TYPE(pDesc, dmaMode, doutAdr, doutSize, axiNs)							\

	do {		                                                                                        	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&U32_MAX );		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], (dmaMode));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));		\
@@ -315,7 +308,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DOUT_DLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd)								\

	do {		                                                                                        		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&U32_MAX );		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_DLLI);			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));			\
@@ -335,7 +328,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DOUT_MLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd)								\

	do {		                                                                                        		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&U32_MAX );		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_MLLI);			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));			\
@@ -354,7 +347,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DOUT_NO_DMA(pDesc, doutAdr, doutSize, registerWriteEnable)							\

	do {		                                                                                        		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr));			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (u32)(doutAdr));			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));			\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], (registerWriteEnable));	\

	} while (0)
@@ -367,7 +360,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_XOR_VAL(pDesc, xorVal)										\

	do {		                                                                                        	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(xorVal));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (u32)(xorVal));		\

	} while (0)



/*!
@@ -401,7 +394,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_DOUT_SRAM(pDesc, doutAdr, doutSize)									\

	do {		                                                                                        	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (u32)(doutAdr));		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_SRAM);		\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));		\

	} while (0)
@@ -415,7 +408,7 @@ typedef enum HwDesKeySize { 
 */

#define HW_DESC_SET_XEX_DATA_UNIT_SIZE(pDesc, dataUnitSize)								\

	do {														\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(dataUnitSize));	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (u32)(dataUnitSize));	\

	} while (0)



/*!
@@ -426,7 +419,7 @@ typedef enum HwDesKeySize { 
*/

#define HW_DESC_SET_MULTI2_NUM_ROUNDS(pDesc, numRounds)									\

	do {														\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(numRounds));	\

		CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (u32)(numRounds));	\

	} while (0)



/*!

drivers/staging/ccree/cc_lli_defs.h

+5 −5
Original line number Diff line number Diff line
@@ -29,18 +29,18 @@ 


#define CC_MAX_MLLI_ENTRY_SIZE 0x10000



#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&UINT16_MAX)

#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&U16_MAX)



#define LLI_SET_ADDR(lli_p, addr) \

		BITFIELD_SET(((uint32_t *)(lli_p))[LLI_WORD0_OFFSET], LLI_LADDR_BIT_OFFSET, LLI_LADDR_BIT_SIZE, (addr & UINT32_MAX)); \

		BITFIELD_SET(((uint32_t *)(lli_p))[LLI_WORD1_OFFSET], LLI_HADDR_BIT_OFFSET, LLI_HADDR_BIT_SIZE, MSB64(addr));

		BITFIELD_SET(((u32 *)(lli_p))[LLI_WORD0_OFFSET], LLI_LADDR_BIT_OFFSET, LLI_LADDR_BIT_SIZE, (addr & U32_MAX)); \

		BITFIELD_SET(((u32 *)(lli_p))[LLI_WORD1_OFFSET], LLI_HADDR_BIT_OFFSET, LLI_HADDR_BIT_SIZE, MSB64(addr));



#define LLI_SET_SIZE(lli_p, size) \

		BITFIELD_SET(((uint32_t *)(lli_p))[LLI_WORD1_OFFSET], LLI_SIZE_BIT_OFFSET, LLI_SIZE_BIT_SIZE, size)

		BITFIELD_SET(((u32 *)(lli_p))[LLI_WORD1_OFFSET], LLI_SIZE_BIT_OFFSET, LLI_SIZE_BIT_SIZE, size)



/* Size of entry */

#define LLI_ENTRY_WORD_SIZE 2

#define LLI_ENTRY_BYTE_SIZE (LLI_ENTRY_WORD_SIZE * sizeof(uint32_t))

#define LLI_ENTRY_BYTE_SIZE (LLI_ENTRY_WORD_SIZE * sizeof(u32))



/* Word0[31:0] = ADDR[31:0] */

#define LLI_WORD0_OFFSET 0

drivers/staging/ccree/cc_regs.h

+2 −2
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 
/* Read-Modify-Write a field of a register */

#define MODIFY_REGISTER_FLD(unitName, regName, fldName, fldVal)         \

do {								            \

	uint32_t regVal;						    \

	u32 regVal;						    \

	regVal = READ_REGISTER(CC_REG_ADDR(unitName, regName));       \

	CC_REG_FLD_SET(unitName, regName, fldName, regVal, fldVal); \

	WRITE_REGISTER(CC_REG_ADDR(unitName, regName), regVal);       \
@@ -86,7 +86,7 @@ do { \ 
} while (0)



/* Usage example:

   uint32_t reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL));

   u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL));

   CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3);

   CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1);

   WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow);

drivers/staging/ccree/hash_defs.h

+7 −7
Original line number Diff line number Diff line
@@ -48,13 +48,13 @@ enum HashConfig1Padding { 
	HASH_PADDING_DISABLED = 0,

	HASH_PADDING_ENABLED = 1,

	HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2,

	HASH_CONFIG1_PADDING_RESERVE32 = INT32_MAX,

	HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX,

};



enum HashCipherDoPadding {

	DO_NOT_PAD = 0,

	DO_PAD = 1,

	HASH_CIPHER_DO_PADDING_RESERVE32 = INT32_MAX,

	HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,

};



typedef struct SepHashPrivateContext {
@@ -66,11 +66,11 @@ typedef struct SepHashPrivateContext { 
	   This means that this structure size (without the reserved field can be up to 20 bytes ,

	   in case sha512 is not suppported it is 20 bytes (SEP_HASH_LENGTH_WORDS define to 2 ) and in the other

	   case it is 28 (SEP_HASH_LENGTH_WORDS define to 4) */

	uint32_t reserved[(sizeof(struct drv_ctx_hash)/sizeof(uint32_t)) - SEP_HASH_LENGTH_WORDS - 3];

	uint32_t CurrentDigestedLength[SEP_HASH_LENGTH_WORDS];

	uint32_t KeyType;

	uint32_t dataCompleted;

	uint32_t hmacFinalization;

	u32 reserved[(sizeof(struct drv_ctx_hash)/sizeof(u32)) - SEP_HASH_LENGTH_WORDS - 3];

	u32 CurrentDigestedLength[SEP_HASH_LENGTH_WORDS];

	u32 KeyType;

	u32 dataCompleted;

	u32 hmacFinalization;

	/* no space left */

} SepHashPrivateContext_s;

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